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75 lines
3.2 KiB
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75 lines
3.2 KiB
ReStructuredText
.. meta::
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:description: Device software glossary for AMD GPUs
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:keywords: AMD, ROCm, GPU, device software, programming model, AMDGPU,
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assembly, IR, GFX IP, wavefront, work-group, HIP kernel, thread hierarchy
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.. _glossary-device-software:
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************************
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Device software glossary
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************************
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This section provides brief definitions of software abstractions and programming
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models that run on AMD GPUs.
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.. glossary::
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:sorted:
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ROCm programming model
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The ROCm programming model defines how AMD GPUs execute massively
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parallel programs using hierarchical
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:term:`work-groups <Work-group (Block)>`, memory scopes, and barrier
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synchronization. See :ref:`hip:programming_model` for complete details.
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AMDGPU assembly
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AMDGPU assembly (GFX ISA) is the low-level assembly format for programs
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running on AMD GPUs, generated by the
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:term:`ROCm compiler toolchain <HIP compiler>`. See
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:ref:`hip:amdgpu_assembly` for instruction set details.
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AMDGPU intermediate representation
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AMDGPU IR is an intermediate representation for GPU code, serving as a
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virtual instruction set between high-level languages and
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:term:`architecture-specific assembly <AMDGPU assembly>`. See
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:ref:`hip:amdgpu_ir` for compilation details.
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LLVM target name
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The LLVM target name is a string identifier corresponding to a specific
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:term:`GFX IP <GFX IP>` version that is passed to the
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:term:`HIP compiler <HIP compiler>` toolchain to specify the target GPU
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architecture for code generation.
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See :doc:`llvm-project:reference/rocmcc` for details.
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Grid
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A grid represents the collection of all
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:term:`work-groups <Work-group (Block)>` executing a single
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:term:`kernel <HIP kernel>` across the entire GPU. See
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:ref:`hip:inherent_thread_hierarchy_grid` for grid execution details.
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HIP kernel
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A HIP kernel is the unit of GPU code that executes in parallel across
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many :term:`threads <Work-item (Thread)>`, distributed across the GPU's
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:term:`compute units <Compute units>`. See :ref:`hip:device_program` for
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kernel programming details.
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HIP thread hierarchy
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The thread hierarchy structures parallel work from individual
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:term:`threads <Work-item (Thread)>` to
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:term:`blocks <Work-group (Block)>` to :term:`grids <Grid>`, mapping
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onto hardware from :term:`SIMD lanes <SIMD core>` to
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:term:`compute units <Compute units>` to the entire GPU. See
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:ref:`hip:inherent_thread_model` for complete details.
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HIP memory hierarchy
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The memory hierarchy pairs each
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:term:`thread hierarchy <HIP thread hierarchy>` level with corresponding
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memory scopes, from :term:`private registers <Register>` to
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:term:`LDS <Local data share>` to :term:`GPU RAM <GPU RAM (VRAM)>`. See
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:ref:`hip:memory_hierarchy` for memory architecture details.
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Global memory
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Global memory is the :term:`device-wide memory <GPU RAM (VRAM)>`
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accessible to all :term:`threads <Work-item (Thread)>`, physically
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implemented as HBM or GDDR. See :ref:`hip:memory_hierarchy` for global
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memory details.
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