papers/lightspeed-dex/sections/06-performance-optimizations.tex

\section{Performance Optimizations}


\subsection{Low-Latency Networking}

\textbf{Dedicated fiber}: Direct connections between data centers
\begin{itemize}
    \item NY4 $\leftrightarrow$ LD8: 76ms (transatlantic fiber)
    \item LD8 $\leftrightarrow$ CC2: 230ms (via Middle East route)
    \item NY4 $\leftrightarrow$ CC2: 140ms (transpacific fiber)
\end{itemize}

\textbf{Microwave links}: For ultra-low latency (NY4 $\leftrightarrow$ Chicago: 8ms vs 14ms fiber).

\subsection{Hardware Acceleration}

\textbf{FPGA order matching}:
\begin{itemize}
    \item Xilinx Alveo U250 cards
    \item 10 Gbps throughput
    \item $<$1$\mu$s matching latency
    \item Deterministic execution (no CPU jitter)
\end{itemize}

\begin{table}[h]
\centering
\begin{tabular}{lrr}
\toprule
\textbf{Component} & \textbf{CPU ($\mu$s)} & \textbf{FPGA ($\mu$s)} \\
\midrule
Order parsing & 2.5 & 0.1 \\
Matching engine & 15.0 & 0.5 \\
State update & 8.0 & 0.3 \\
\textbf{Total} & \textbf{25.5} & \textbf{0.9} \\
\bottomrule
\end{tabular}
\caption{CPU vs FPGA latency for order processing}
\end{table}

\textbf{28$\times$ speedup} with FPGA acceleration.

\subsection{Memory Optimization}

\textbf{In-memory order books}: No disk I/O during matching.

\begin{lstlisting}[language=Go]
type OrderBook struct {
    Bids *SkipList  // Price-time ordered
    Asks *SkipList
    Cache map[OrderID]*Order  // O(1) lookup
}

// Average case: O(log n) insert, O(1) top-of-book
\end{lstlisting}

\textbf{Memory requirements}:
\begin{itemize}
    \item 1M orders: 100 MB (100 bytes/order)
    \item 256 shards: 25.6 GB total
    \item Validators: 64 GB RAM (comfortable headroom)
\end{itemize}