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This change enables 5-level paging by supporting P4D table. During PageTable.InitArch(), we detect CPU capabilities and set a flag to determine the paging mode. Update iterateRangeCanonical() call handle P4D level. We avoid using a separate walkP4D function because the call chain would be too deep for the nosplit attribute. The P4D level logic is wrapped around a if/else statement for clarity PiperOrigin-RevId: 800161142
125 lines
4.1 KiB
Go
125 lines
4.1 KiB
Go
// Copyright 2018 The gVisor Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//go:build amd64
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// +build amd64
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package pagetables
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import (
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"testing"
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"gvisor.dev/gvisor/pkg/cpuid"
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"gvisor.dev/gvisor/pkg/hostarch"
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)
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var (
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lowerTopAligned uintptr = 0x00007f0000000000
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pt *PageTables
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)
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func getLargeAddressesEnabled() bool {
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featureSet := cpuid.HostFeatureSet()
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return featureSet.HasFeature(cpuid.X86FeatureLA57)
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}
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func getLowerTopAligned() uintptr {
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if getLargeAddressesEnabled() {
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return 0x00FF000000000000
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}
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return lowerTopAligned
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}
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func InitTest() {
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cpuid.Initialize()
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pt = New(NewRuntimeAllocator())
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pt.InitArch(NewRuntimeAllocator())
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}
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func TestLargeAddresses(t *testing.T) {
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InitTest()
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if !getLargeAddressesEnabled() {
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t.Skip("Large addresses are not supported on this platform")
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}
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pt.Map(hostarch.Addr(1<<50), pteSize, MapOpts{AccessType: hostarch.ReadWrite}, pteSize*42)
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pt.Map(hostarch.Addr(1<<54), pmdSize, MapOpts{AccessType: hostarch.Read}, pmdSize*42)
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checkMappings(t, pt, []mapping{
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{uintptr(1 << 50), pteSize, pteSize * 42, MapOpts{AccessType: hostarch.ReadWrite}},
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{uintptr(1 << 54), pmdSize, pmdSize * 42, MapOpts{AccessType: hostarch.Read}},
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})
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}
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func Test2MAnd4K(t *testing.T) {
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InitTest()
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// Map a small page and a huge page.
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pt.Map(0x400000, pteSize, MapOpts{AccessType: hostarch.ReadWrite}, pteSize*42)
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pt.Map(hostarch.Addr(getLowerTopAligned()), pmdSize, MapOpts{AccessType: hostarch.Read}, pmdSize*47)
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checkMappings(t, pt, []mapping{
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{0x400000, pteSize, pteSize * 42, MapOpts{AccessType: hostarch.ReadWrite}},
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{getLowerTopAligned(), pmdSize, pmdSize * 47, MapOpts{AccessType: hostarch.Read}},
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})
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}
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func Test1GAnd4K(t *testing.T) {
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InitTest()
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// Map a small page and a super page.
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pt.Map(0x400000, pteSize, MapOpts{AccessType: hostarch.ReadWrite}, pteSize*42)
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pt.Map(hostarch.Addr(getLowerTopAligned()), pudSize, MapOpts{AccessType: hostarch.Read}, pudSize*47)
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checkMappings(t, pt, []mapping{
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{0x400000, pteSize, pteSize * 42, MapOpts{AccessType: hostarch.ReadWrite}},
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{getLowerTopAligned(), pudSize, pudSize * 47, MapOpts{AccessType: hostarch.Read}},
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})
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}
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func TestSplit1GPage(t *testing.T) {
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InitTest()
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// Map a super page and knock out the middle.
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pt.Map(hostarch.Addr(getLowerTopAligned()), pudSize, MapOpts{AccessType: hostarch.Read}, pudSize*42)
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pt.Unmap(hostarch.Addr(getLowerTopAligned()+pteSize), pudSize-(2*pteSize))
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checkMappings(t, pt, []mapping{
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{getLowerTopAligned(), pteSize, pudSize * 42, MapOpts{AccessType: hostarch.Read}},
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{getLowerTopAligned() + pudSize - pteSize, pteSize, pudSize*42 + pudSize - pteSize, MapOpts{AccessType: hostarch.Read}},
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})
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}
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func TestSplit2MPage(t *testing.T) {
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InitTest()
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// Map a huge page and knock out the middle.
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pt.Map(hostarch.Addr(getLowerTopAligned()), pmdSize, MapOpts{AccessType: hostarch.Read}, pmdSize*42)
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pt.Unmap(hostarch.Addr(getLowerTopAligned()+pteSize), pmdSize-(2*pteSize))
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checkMappings(t, pt, []mapping{
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{getLowerTopAligned(), pteSize, pmdSize * 42, MapOpts{AccessType: hostarch.Read}},
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{getLowerTopAligned() + pmdSize - pteSize, pteSize, pmdSize*42 + pmdSize - pteSize, MapOpts{AccessType: hostarch.Read}},
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})
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}
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func TestNumMemoryTypes(t *testing.T) {
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InitTest()
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// The PAT accommodates up to 8 entries. However, PTE.Set() currently
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// assumes that NumMemoryTypes <= 4, since the location of the most
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// significant bit of the PAT index in page table entries varies depending
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// on page size (and is never bit 5 == writeThroughShift + 2).
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if hostarch.NumMemoryTypes > 4 {
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t.Errorf("PTE.Set() and PTE.Opts() must be altered to handle %d MemoryTypes", hostarch.NumMemoryTypes)
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}
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}
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