mirror of
https://github.com/hanzoai/visor.git
synced 2026-09-24 17:04:14 +00:00
Tao Lin
a9f716e19e
- Update copyright year to 2026 for all new files - Update comment in hostarch_arm64.go to mention 64K page support via pagesize_64k build tag - Add PageSize checks in KVM and Systrap New() constructors to fail early on non-4K page sizes
54 lines
1.6 KiB
Go
54 lines
1.6 KiB
Go
// Copyright 2026 The gVisor Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//go:build arm64 && pagesize_64k
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package pagetables
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// Page table constants for 64K page size (3-level page tables).
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//
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// With 64K pages, we use a 3-level page table structure:
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// - PGD (Page Global Directory)
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// - PMD (Page Middle Directory)
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// - PTE (Page Table Entry)
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//
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// Each page table page contains 8192 entries (64K / 8 bytes).
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// Each level uses 13 bits for indexing.
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//
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// Virtual address layout (48-bit):
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// [47:42] - PGD index (6 bits, 64 entries at top level)
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// [41:29] - PMD index (13 bits, 8192 entries)
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// [28:16] - PTE index (13 bits, 8192 entries)
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// [15:0] - Page offset (16 bits, 64K page)
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const (
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pteShift = 16
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pmdShift = 29
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pgdShift = 42
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// Mask for 13-bit index (8192 entries)
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pteMask = 0x1fff << pteShift
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pmdMask = 0x1fff << pmdShift
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// Top level only has 6 bits (64 entries) for 48-bit VA
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pgdMask = 0x3f << pgdShift
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pteSize = 1 << pteShift // 64K
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pmdSize = 1 << pmdShift // 512M
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pgdSize = 1 << pgdShift // 4T
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entriesPerPage = 8192
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)
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// PTEs is a collection of entries.
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type PTEs [entriesPerPage]PTE
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