Files
wasm2go/internal/gcasm/simdsplice_fuse_dot8_x64.go
b7b7026cc5 gcasm: amd64 cross-chain raw dots for the repack kernels + F16C scale conversion (#62)
* gcasm: fuse the interleaved repack kernels' cross-chain dots on amd64; F16C scale conversion

The ggml q8_0x4 repack gemv/gemm keeps two i32x4_add chains per
block — all extend_low half dots in one, all extend_high in the
other, over the same byte-source pairs — and combines them with the
even/odd dword-select shuffles. The existing (low, high) pairing walk
never fires on that shape, so amd64 ran it as literal SSE pair ops
while arm64's a64CrossSdotRewrite turned it into raw SDOT chains.

x64CrossDotRewrite is the amd64 twin: it matches the combine on the
raw node forms and rebuilds it as a chain of synthetic raw block
dots. Emission computes each 16-byte leaf in the 8-lane VPMADDWD
domain across one ymm and collapses to the four-consecutive-byte
grouping in-register (VPHADDD + VEXTRACTI128 + VPUNPCKLQDQ), then
VPADDD-accumulates. i16 products of i8 lanes cannot overflow and
VPMADDWD widens into i32, so every step is exact for ALL inputs —
unlike the VPSIGNB/VPMADDUBSW route native kernels use, which wraps
on -128 — and i32 wraparound addition is associative, so regrouping
is bit-identical. Feature-body only; portable twins keep the SSE
lowering via the existing dual-body dispatch.

f16x4_cvt feature bodies now convert with mask + VPACKUSDW +
VCVTPH2PS (F16C, which the HasAVX2 gate already requires) instead of
the 15-op SSE2 bit trick — the x64 mirror of the arm64 xtn+fcvtl
pair. Both sequences are all-VEX-128, so x64TreeVexClean treats them
as clean and no ymm upper state is dirtied.

Co-Authored-By: Claude Fable 5 <[email protected]>

* gcasm: pair-domain wide raw-dot chains; skip the dead f16 mask after zero-extending loads

The per-leaf raw-dot emission collapsed every 16-byte leaf through
VPHADDD-ymm + VEXTRACTI128 — three lane-crossing shuffles per leaf,
the exact shape the earlier chunk-widening experiment measured as a
loss on Zen 3. The chain now accumulates in the 8-lane VPMADDWD pair
domain across a full ymm (four ops per leaf, only the two unavoidable
VPMOVSXBW crossings) and collapses ONCE per chain at the combine
slot. The running value's ymm upper must survive between links, so
the wide form is selected only for fully-VEX trees (region-exit
VZEROUPPER, every other write VEX); anything else falls back to the
self-contained per-leaf form. Exactness is unchanged: same integer
products, i32 add reassociation only.

f16x4_cvt over v128_load16x4_u drops its VPAND: the load
zero-extends, so the lanes' upper halves are already empty and
VPACKUSDW packs them exactly.

Co-Authored-By: Claude Fable 5 <[email protected]>

* codegen: fuse loops whose leftover interveners derive from bumped arguments or died into the tree

The interleaved repack kernels' inner loops matched the countdown
shape, window-fused their whole body, and carried their accumulators
— then failed the final leftover-intervener invariance check on two
statement kinds and fell back to the per-iteration window path, whose
region boundaries (result parking, VZEROUPPER, argument
re-materialization, scalar glue) dominate the prompt-processing
profile on both arches:

- a derived address ("q = p + off", one or two levels deep) whose
  argument slot can simply take p's own bump: the hoisted initial
  reads p's pre-loop value, which is exactly the slot's base, and the
  slot then advances in lockstep. The existing reassociation only
  covered bump targets that are not arguments themselves.
- a value whose only readers were CONSUMED into the fused tree (the
  tree recomputes it through its own scalar chain — the f16 LUT index
  load): dead once the loop fuses, droppable.

On the llama engine this upgrades the four hot repack gemv loops
(plus one more) to fused loops; previously only one loop in the whole
module fused.

Co-Authored-By: Claude Fable 5 <[email protected]>

* gcasm: hoist fused-loop window checks for floor loops and chain-addressed narrow loads

The loop-level window-check hoist only covered pretest power-of-two
loops and rng-windowed loads with plain scalar bases. The interleaved
repack loops are do-while floor loops (unit step, signed threshold
backedge) whose loads address through scalar-chain sums
(bumpedBase + columnBase + const) — every load kept its 7-op
per-iteration bounds/address dance, which the profile puts at the
top of what remains after loop fusion.

- Iteration-count form 2: a do-while ExitGT unit-step loop runs
  max(counter - thresh, 1) iterations, so iters-1 =
  counter - thresh - 1 clamped at zero — computable at entry.
- Address resolution generalizes to affine chains: ArgScalar/ArgSum
  or a scalar_i32_add tree over them; the stride is the sum of the
  terms' bump deltas, and one check per (terms, end, stride) family
  covers every load in it.
- Narrow loads join the rewrite through unchecked twins
  (v128_load32_splat_nc / load16x4_u_nc / load32_zero_nc /
  load64_zero_nc, x64-splicer-local), all emitting single folded
  indexed instructions; a full-width chain already terminating in
  R12 also drops its redundant self-move.

Co-Authored-By: Claude Fable 5 <[email protected]>

* gcasm: retarget the repack GEMM to native 4x4 tile kernels

The engine's wasm-side q8_0x4 GEMM (exported as dbg_gemm_q8_0_4x4
exactly so the transpiler can find it) is shaped as four sequential
gemv passes — the form the loop fusion is proven to claim — which
gives up the tile's 4x weight reuse: prompt processing runs at
token-generation speed per token.

The whole feature body now becomes a native 4x4 tile kernel through
the existing dual-body dispatch (portable twin = the transformed wasm
body):

- arm64: by-element SDOT — the activation block interleaves the four
  rows' 4-byte groups contiguously, so each 16-byte weight group is
  one load + four `sdot vAcc.4s, vW.16b, vA.4b[row]`, the native
  dotprod kernel's own shape. Gated on CPUDotProd.
- amd64: AVX2 nest sign-extends each weight group once per ymm and
  runs four broadcast-activation VPMADDWD accumulations against it;
  a VNNI entry branch uses VPDPBUSD with the exact +128 bias
  identity, with the per-row byte sums accumulated by ONE extra
  VPDPBUSD per group (ones dot the activation block yields all four
  rows' group sums). Gated on HasAVX2 / gcasmHasAVX512VNNI.

Integer arithmetic is exact; the per-block scale accumulation keeps
the sequential form's per-row block order but fuses mul+add, so the
retarget is fast-math-only, like the nrc2 tile kernel. Every span the
loop nest will touch is bounds-checked against memSize at entry.

Both kernels assemble and link on every host in the new gate tests;
the numeric comparison against a scalar reference executes on
matching hosts (the arm64 kernel passes natively on Apple Silicon;
CI's amd64 runner executes the AVX2 arm).

Co-Authored-By: Claude Fable 5 <[email protected]>

* gcasm: repack GEMM kernels keep the wasm's own mul/add rounding; opt-out env

The tile kernels' per-block scale accumulation switches from fused
multiply-add to the exact multiply/multiply/add sequence the wasm
gemm (and the fused GEMV loops) execute, so the batched path rounds
identically to the wasm semantics it replaces — keeping the batched
and single-row prompt paths as close as the engine's own contract.
(The prompt batch-size divergence observed with qwen on arm64
reproduces byte-for-byte on the PREVIOUS engine as well: it is the
known batched-vs-incremental near-tie flip, not a kernel effect.)

WASM2GO_NO_REPACK_GEMM=1 disables the retarget for A/B bisection,
mirroring the other WASM2GO_* iteration toggles.

Co-Authored-By: Claude Fable 5 <[email protected]>

* lower: pin the exported repack GEMM out-of-line so its retarget stays live

wasm2go's own function inliner (leaf, <=4096 bytes) was splicing the
exported dbg_gemm_q8_0_4x4 body into its caller
(forward_mul_mat_one_chunk), so the standalone body the gcasm backend
retargets to the native 4x4 tile kernel was dead — the tile never
ran, and pp went through the inlined per-pass GEMV shape instead.
(Binaryen was not involved: -Oz leaves the wasm-level calls intact.)

The inliner now pins any dbg_gemm_-exported function out-of-line
regardless of size. GEMV is deliberately left inlinable: it runs at
nrows=1 in the decode hot path, where per-call overhead outweighs the
tile — pinning it out-of-line measured a tg regression, so only the
batched GEMM is pinned.

Co-Authored-By: Claude Fable 5 <[email protected]>

* gcasm: deduplicate shared emission shapes in the amd64 repack work

Pure refactor — emitted assembly is byte-identical (verified by
dumping every touched emission path before and after):

- Promote the even/odd dword-select shuffle classifier out of
  a64CrossSdotRewrite into package-level crossSelKind and drop the
  verbatim x64 copy; the patterns are wasm-level constants shared by
  both arch rewrites.
- Extract x64PairFold for the VPHADDD/VEXTRACTI128/VPUNPCKLQDQ
  pair-domain collapse emitted from three sites.
- Merge the four unchecked narrow-load cases in x64FusedLoad into one
  table-shaped case (VMOVSS/VMOVQ plus the op's own widen).
- Replace the hand-rolled insertion sort in x64CrossDotRewrite with
  sort.Slice over the leaf records used directly.
- Share the repack GEMM ABI0 argument frame layout between the a64
  and x64 emitters (repackGemmArgs).
- Build the per-arch trapstub once in writeGemmRunTree instead of
  writing the amd64 kernel file twice.

Co-Authored-By: Claude Opus 4.8 <[email protected]>

* gcasm: make the repack GEMM opt-out a config option, not an env var

Replace the WASM2GO_NO_REPACK_GEMM environment check with
DisableRepackGemm threaded through the option structs — the project's
configuration pattern (codegen.Options -> gcasm.Config, CLI flag
-no-repack-gemm). The retarget-target scan moves into
repackGemmExport with a unit test over the gate combinations.

Co-Authored-By: Claude Opus 4.8 <[email protected]>

---------

Co-authored-by: Claude Fable 5 <[email protected]>
2026-09-02 19:13:26 +09:00

345 lines
11 KiB
Go

package gcasm
import (
"github.com/goccy/wasm2go/internal/simdfuse"
)
// AVX2 8-bit dot selection (amd64).
//
// The quantized integer kernels compute, per 16-byte chunk, the two
// half dots
//
// dot(extend_low_i8x16_s(a), extend_low_i8x16_s(b))
// dot(extend_high_i8x16_s(a), extend_high_i8x16_s(b))
//
// and sum them into an i32x4 accumulator chain. The SSE baseline
// lowers each half literally (~9 xmm ops per chunk). AVX2 does the
// whole chunk in one 256-bit pass: VPMOVSXBW sign-extends all 16
// bytes of a (and of b) into a ymm of 16 i16 lanes, VPMADDWD
// multiplies and pair-adds them into 8 i32 lanes — lanes 0..3 are
// exactly the low-half dot, lanes 4..7 the high-half — and
// VEXTRACTI128 + VPADDD fold the high 128 onto the low 128. int8*int8
// fits i16 and the pair sums fit i32, so no lane saturates; i32
// addition is associative, so re-grouping the chain's adds is
// bit-identical to the literal lowering. Five ops replace nine.
//
// The two halves of a chunk are NOT always direct siblings under one
// add: the unrolled kernels emit left-leaning chains where a chunk's
// low and high dots join the accumulator spine separately
// (add(add(prev, dot_high_B), dot_low_B)). So, like the arm64
// a64Dot8FlattenAdds, the rewrite walks each maximal i32x4_add tree
// whose leaves are all eligible half dots, pairs the leaves by their
// byte-source pair (one low + one high over the same (a, b)), and
// rebuilds the chain over the paired block dots plus any unpaired
// half dots left literal.
//
// The rewrite runs on a local copy of the tree at splice time; every
// absorbed node becomes a no-op placeholder (a64OpElided) so node
// indices stay stable for roots and loop-carried bookkeeping.
// portable (the baseline-ISA twin body) suppresses it, so a non-AVX2
// host runs the literal SSE path.
const (
// x64OpBlockDot(a, b): the full 16-byte signed 8-bit dot of two
// byte vectors — four i32 lanes, each the sum of its four byte
// products (the value of dot_low + dot_high for the chunk).
x64OpBlockDot = "i32x4_blockdot8_avx2"
)
// x64Dot8Src reports whether a byte source can feed the synthetic
// block dot directly: a member's register-resident result or a pair
// input (mirrors a64Dot8Src).
func x64Dot8Src(a simdfuse.Arg) bool {
return a.Kind == simdfuse.ArgNode || a.Kind == simdfuse.ArgPairIn
}
// x64HalfDot describes one eligible half dot: an i32x4_dot_i16x8_s
// whose operands are both extend_low (high=false) or both extend_high
// (high=true) of register-readable byte sources.
type x64HalfDot struct {
dot int // the dot node
e0, e1 int // the two extend nodes it consumes
srcA, srcB simdfuse.Arg
high bool
}
// x64ClassifyHalfDot classifies node k, requiring the extends to exist
// solely for this dot (single use, not a region result).
func x64ClassifyHalfDot(nodes []simdfuse.Node, uses []int, isRoot []bool, k int) (x64HalfDot, bool) {
n := &nodes[k]
if n.Op != "i32x4_dot_i16x8_s" || len(n.Args) != 2 {
return x64HalfDot{}, false
}
a0, a1 := n.Args[0], n.Args[1]
if a0.Kind != simdfuse.ArgNode || a1.Kind != simdfuse.ArgNode || a0.Index == a1.Index {
return x64HalfDot{}, false
}
e0, e1 := &nodes[a0.Index], &nodes[a1.Index]
var high bool
switch {
case e0.Op == "i16x8_extend_low_i8x16_s" && e1.Op == "i16x8_extend_low_i8x16_s":
high = false
case e0.Op == "i16x8_extend_high_i8x16_s" && e1.Op == "i16x8_extend_high_i8x16_s":
high = true
default:
return x64HalfDot{}, false
}
if uses[a0.Index] != 1 || uses[a1.Index] != 1 || isRoot[a0.Index] || isRoot[a1.Index] {
return x64HalfDot{}, false
}
if len(e0.Args) != 1 || len(e1.Args) != 1 || !x64Dot8Src(e0.Args[0]) || !x64Dot8Src(e1.Args[0]) {
return x64HalfDot{}, false
}
return x64HalfDot{dot: k, e0: a0.Index, e1: a1.Index, srcA: e0.Args[0], srcB: e1.Args[0], high: high}, true
}
// x64SrcKey is a comparable byte-source pair identity.
type x64SrcKey struct {
ka, kb simdfuse.ArgKind
ia, ib int
}
func x64KeyOf(h x64HalfDot) x64SrcKey {
return x64SrcKey{ka: h.srcA.Kind, ia: h.srcA.Index, kb: h.srcB.Kind, ib: h.srcB.Index}
}
// x64Dot8Rewrite returns the tree with chunk half-dot pairs collapsed
// into synthetic AVX2 block dots, and reports whether it rewrote
// anything (the caller emits one VZEROUPPER when it did). The tree is
// returned unchanged when nothing matches or portable suppresses the
// upgrade.
func x64Dot8Rewrite(tree *simdfuse.Tree, portable bool) (*simdfuse.Tree, bool) {
if portable {
return tree, false
}
uses := make([]int, len(tree.Nodes))
for _, n := range tree.Nodes {
for _, a := range n.Args {
if a.Kind == simdfuse.ArgNode {
uses[a.Index]++
}
}
}
isRoot := make([]bool, len(tree.Nodes))
for _, r := range tree.RootList() {
isRoot[r] = true
}
nodes := append([]simdfuse.Node(nil), tree.Nodes...)
consumed := make([]bool, len(nodes))
rewrote := false
// Walk tops in DESCENDING index so each maximal add tree is claimed
// from its outermost add (mirrors a64Dot8FlattenAdds).
for t := len(nodes) - 1; t >= 0; t-- {
if consumed[t] || !isAddAny(nodes, t) {
continue
}
var leaves []x64HalfDot
var adds []int
// The chain may carry AT MOST ONE non-dot value — the running
// accumulator (a loop-carried pair input, or any prior node) the
// kernels fold each chunk into. It rides the rebuilt chain like
// any other leaf; i32 adds are associative, so its position is
// free.
var extra []simdfuse.Arg
ok := true
var walk func(a simdfuse.Arg)
walk = func(a simdfuse.Arg) {
if !ok {
return
}
if a.Kind == simdfuse.ArgNode {
i := a.Index
if isAddAny(nodes, i) && i != t && uses[i] == 1 && !isRoot[i] && !consumed[i] {
adds = append(adds, i)
walk(nodes[i].Args[0])
walk(nodes[i].Args[1])
return
}
if h, hok := x64ClassifyHalfDot(nodes, uses, isRoot, i); hok && uses[i] == 1 && !isRoot[i] {
leaves = append(leaves, h)
return
}
}
// Non-dot leaf (accumulator or anything else): one allowed.
if len(extra) == 0 {
extra = append(extra, a)
return
}
ok = false
}
adds = append(adds, t)
walk(nodes[t].Args[0])
walk(nodes[t].Args[1])
if !ok || len(leaves) < 2 || len(adds) != len(leaves)+len(extra)-1 {
continue
}
// Pair one low with one high per byte-source pair.
lows := map[x64SrcKey][]int{} // leaf index in leaves
highs := map[x64SrcKey][]int{}
for li, h := range leaves {
if h.high {
highs[x64KeyOf(h)] = append(highs[x64KeyOf(h)], li)
} else {
lows[x64KeyOf(h)] = append(lows[x64KeyOf(h)], li)
}
}
type pair struct{ low, high x64HalfDot }
var pairs []pair
paired := make([]bool, len(leaves))
for k, ls := range lows {
hs := highs[k]
for len(ls) > 0 && len(hs) > 0 {
pairs = append(pairs, pair{low: leaves[ls[0]], high: leaves[hs[0]]})
paired[ls[0]], paired[hs[0]] = true, true
ls, hs = ls[1:], hs[1:]
}
}
if len(pairs) == 0 {
continue
}
// The rebuilt chain's values: each pair's block dot lives in the
// lower-indexed dot slot (its byte sources index below both
// dots); unpaired half dots stay literal; the extra leaf (the
// accumulator) rides along as-is.
var newLeaves []simdfuse.Arg
for _, p := range pairs {
bd := p.low.dot
if p.high.dot < bd {
bd = p.high.dot
}
newLeaves = append(newLeaves, simdfuse.Arg{Kind: simdfuse.ArgNode, Index: bd})
}
for li, h := range leaves {
if !paired[li] {
newLeaves = append(newLeaves, simdfuse.Arg{Kind: simdfuse.ArgNode, Index: h.dot})
}
}
newLeaves = append(newLeaves, extra...)
// Order by node index (non-node leaves first: they have no
// position constraint).
sortArgsByIndex(newLeaves)
sortInts(adds)
// availableAt reports whether arg a may be referenced from a
// chain node at index slot (post-order: node args index below).
availableAt := func(a simdfuse.Arg, slot int) bool {
return a.Kind != simdfuse.ArgNode || a.Index < slot
}
if len(newLeaves) == 1 {
// Single pair, nothing else: the block dot must live at t
// itself (its consumers reference t); its byte sources index
// below every dot, so post-order holds.
p := pairs[0]
nodes[t] = simdfuse.Node{Op: x64OpBlockDot, Args: []simdfuse.Arg{p.low.srcA, p.low.srcB}}
x64ElidePair(nodes, p.low, p.high, -1)
for _, a := range adds {
if a != t {
nodes[a] = simdfuse.Node{Op: a64OpElided}
}
consumed[a] = true
}
rewrote = true
continue
}
// Rebuild into the LARGEST len(newLeaves)-1 add slots (ending at
// t); verify post-order before mutating.
used := adds[len(adds)-(len(newLeaves)-1):]
valid := true
prev := newLeaves[0]
for j, slot := range used {
if !availableAt(prev, slot) || !availableAt(newLeaves[j+1], slot) {
valid = false
break
}
prev = simdfuse.Arg{Kind: simdfuse.ArgNode, Index: slot}
}
if !valid {
continue
}
// Mutate: block dots, elisions, then the rebuilt chain.
for _, p := range pairs {
bd := p.low.dot
if p.high.dot < bd {
bd = p.high.dot
}
nodes[bd] = simdfuse.Node{Op: x64OpBlockDot, Args: []simdfuse.Arg{p.low.srcA, p.low.srcB}}
x64ElidePair(nodes, p.low, p.high, bd)
}
usedSet := map[int]bool{}
for _, u := range used {
usedSet[u] = true
}
prev = newLeaves[0]
for j, slot := range used {
nodes[slot] = simdfuse.Node{Op: "i32x4_add", Args: []simdfuse.Arg{prev, newLeaves[j+1]}}
prev = simdfuse.Arg{Kind: simdfuse.ArgNode, Index: slot}
}
for _, a := range adds {
if !usedSet[a] {
nodes[a] = simdfuse.Node{Op: a64OpElided}
}
consumed[a] = true
}
rewrote = true
}
// Cross-chain shapes (separate all-low/all-high chains joined by
// the even/odd shuffle combine — the interleaved repack kernels)
// are untouched by the pairing walk above; upgrade them to raw
// block-dot chains. Try the pair-domain wide form first — it
// keeps a live ymm upper between links, which is only sound in a
// fully-VEX region — and fall back to the self-contained per-leaf
// form otherwise.
snapshot := append([]simdfuse.Node(nil), nodes...)
if x64CrossDotRewrite(nodes, isRoot, tree.ConstPairs, true) {
if x64NodesVexClean(nodes) {
rewrote = true
} else {
copy(nodes, snapshot)
if x64CrossDotRewrite(nodes, isRoot, tree.ConstPairs, false) {
rewrote = true
}
}
}
if !rewrote {
return tree, false
}
out := *tree
out.Nodes = nodes
return &out, true
}
// isAddAny reports whether node i is a two-operand i32x4_add of any
// argument kinds (the chain walk itself dispatches per kind).
func isAddAny(nodes []simdfuse.Node, i int) bool {
n := &nodes[i]
return n.Op == "i32x4_add" && len(n.Args) == 2
}
// x64ElidePair blanks a matched pair's absorbed nodes: the four
// extends and whichever dot slot is not keep (the block dot's home).
func x64ElidePair(nodes []simdfuse.Node, low, high x64HalfDot, keep int) {
if low.dot != keep {
nodes[low.dot] = simdfuse.Node{Op: a64OpElided}
}
if high.dot != keep {
nodes[high.dot] = simdfuse.Node{Op: a64OpElided}
}
for _, e := range []int{low.e0, low.e1, high.e0, high.e1} {
nodes[e] = simdfuse.Node{Op: a64OpElided}
}
}
// sortArgsByIndex orders args ascending by node index, with non-node
// args (no position constraint) first.
func sortArgsByIndex(s []simdfuse.Arg) {
key := func(a simdfuse.Arg) int {
if a.Kind != simdfuse.ArgNode {
return -1
}
return a.Index
}
for i := 1; i < len(s); i++ {
for j := i; j > 0 && key(s[j]) < key(s[j-1]); j-- {
s[j], s[j-1] = s[j-1], s[j]
}
}
}