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wasm2go/internal/gcasm/simdsplicepairtab_amd64_gen.go
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Masaaki GoshimaGitHubClaude Fable 5
 f30ec292fd Support the wasm SIMD proposal with native asm lowering (arm64/amd64) (#40) 
* Support the wasm SIMD proposal with native asm lowering (arm64/amd64)

One revision spanning the SIMD (0xfd v128) proposal end to end: SSA
representation, lowering, scalar reference helpers, and a gcasm asm
backend that turns the hot paths into native SIMD — measured on a
full llama.cpp build transpiled to pure Go, which this makes run at
V8-class speed (prompt eval beats V8 on arm64).

Frontend and SSA:
- v128 values are [2]uint64 pairs in little-endian lane order; pure
  ops lower to CSE-able helper calls, memory ops keep statement
  order, v128.const/shuffle ride as [2]uint64 aux. The full scalar
  helper set is the reference semantics (saturation, NaN
  propagation, round-to-even, swizzle OOB, shift masking).
- Exception handling lowers to plain branches instead of
  panic/recover — a check-and-branch after each may-raise call, a
  per-try dispatch block running the catch-clause chain — covering
  the C++-shaped patterns (multi-clause catch, delegate targets,
  rethrow depths) without runtime unwinding, so EH bodies stay
  eligible for the asm backend. This replaces the closure/recover
  lowering that #39 extended; its tests are retained unchanged.
- Giant functions outline into tractable units (whole loops
  included, packed u64 boundaries for v128 values), keeping gc
  compile times and register pressure sane on llama.cpp-sized
  modules.

gcasm backend:
- SIMD helper calls splice inline as native NEON/SSE instead of
  marshalled calls; v128 SSA values travel register-to-register in
  pair form. Call-tree windows fuse into single splices with region
  invariant hoisting, bounds-check coalescing, store sinks and
  scalar-chain internalization; whole countdown loops fuse with an
  in-splice unroll lane.
- Superinstruction selection inside fused regions: 8-bit dot
  patterns (SMULL+SADALP), SDOT for full 16-byte dots, FMUL by
  element, scale-lookup addressing, inlined integer division, the
  software fp32->fp16 idiom lowered to FCVT (both the table-gather
  and the packed store form), and ggml q8_0 row/column pairing via
  the traits nrows patch with an SMMLA 2x2 tile kernel.
- Runtime CPU-feature dispatch gates spliced bodies (dotprod on
  arm64, x86-64-v2 SSE on amd64); WASM2GO_FAST_MATH opts into
  raw-SDOT/FMLA/dual-accumulator forms that trade wasm bit-exactness
  for native-build-style rounding, validated by token-level
  equivalence against native llama.cpp.
- Guard-page linear memory eliminates per-access bounds checks;
  jump tables replace the compare tree for br_table.

Tooling and CI:
- WASM2GO_F16_TABLE asserts the address of ggml's runtime-built f16
  table; the transpiler warns when the asserted address matches no
  gather site (the address moves with every data-layout shift, and a
  stale assertion silently costs ~7% decode throughput).
- The coverage gate runs with -count=1: a cached package result
  merges incomplete coverage data into the -coverpkg profile,
  deflating the total by 10+ points depending on what the runner's
  restored cache contained — the gate must never consume cached
  results.
- Coverage threshold moves to 83% for the enlarged tree; transpile
  output is deterministic and outline rejections are explained in
  the build log.

Co-Authored-By: Claude Fable 5 <[email protected]>

* Replace environment-variable switches with typed Options; drop debug code

Configuration now flows through one channel: transpile.Options gains
OutlineMinValues, SIMDUnroll, FuseLoops, FuseLoopUnroll, F16TableAddr
and FastMath (with matching CLI flags), the gcasm backend receives
them as a Config threaded through ModuleOffsets, and no code path
branches on an environment variable anymore. Integrator entry points
(the wasmify protoc plugin, the CLI) convert their external
configuration into these options exactly once.

Deleted outright, per the no-env rule and because they were
diagnostics rather than build modes:
- every WASM2GO_NO_* kill switch and bisection knob (SSA pass
  disabling, fallback ranges, fuse-window caps, outline limits,
  inliner windows) — git history keeps them for the next hunt;
- every env-gated debug printer (fuse/inline/outline/nrc2/f16/SSA
  dumps and the near-miss tracers) and the capture-tree keepers;
- the dormant multi-exit loop structuring (opt-in, measured slower)
  and the SSA f32->f16 rewrite entry superseded by the gcasm
  peephole (its shared idiom matchers stay for the f16 store pass);
- the runtime WASM2GO_CPU_PORTABLE override in the generated CPU
  feature probes.

The nil-offsets error paths exposed by the threading get nil-safe
Config accessors, and the outline share/v128-min/inliner caps become
plain constants at their measured production values.

Behavior under default options is unchanged: transpiled output for
the non-SIMD and EH fixtures is byte-identical to the previous
commit, and the only SIMD-bundle difference is the removed env check
in the emitted cpufeat runtime files.

Co-Authored-By: Claude Fable 5 <[email protected]>

---------

Co-authored-by: Claude Fable 5 <[email protected]>
2026-08-08 23:28:14 +09:00

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// Code generated by tools/gen-simd-asm/gen.py; DO NOT EDIT.
package gcasm
// x64SimdPairSpliceTab: pair-form op -> complete amd64 inline
// body (native Go asm, SSE, x86-64-v2). Args ride the register
// ABI (AX, BX, CX, DI, SI, R8, ...; float scalars in X0);
// results in (AX, BX) or the scalar register.
var x64SimdPairSpliceTab = map[string][]string{
"f32x4_abs": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstAbs32(SB), X3", "ANDPS X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_add": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "ADDPS X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_ceil": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "ROUNDPS $2, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_convert_i32x4_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "CVTPL2PS X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_convert_i32x4_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU X0, X3", "PSRLL $16, X3", "PSLLL $16, X0", "PSRLL $16, X0", "CVTPL2PS X0, X0", "CVTPL2PS X3, X3", "MOVOU ·simdConst65536f(SB), X4", "MULPS X4, X3", "ADDPS X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_demote_f64x2_zero": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "CVTPD2PS X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_div": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "DIVPS X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_eq": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "CMPPS X1, X0, $0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_extract_lane": {"SHLL $5, CX", "MOVQ AX, R10", "TESTL $64, CX", "CMOVQNE BX, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVL R10, X0"},
"f32x4_floor": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "ROUNDPS $1, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_ge": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "CMPPS X0, X3, $2", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_gt": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "CMPPS X0, X3, $1", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_le": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "CMPPS X1, X0, $2", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_lt": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "CMPPS X1, X0, $1", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_max": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "MAXPS X1, X3", "MOVOU X1, X4", "MAXPS X0, X4", "MOVOU X3, X5", "XORPS X4, X5", "ORPS X5, X3", "SUBPS X5, X3", "MOVOU X3, X5", "CMPPS X5, X5, $3", "ORPS X5, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_min": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "MINPS X1, X3", "MOVOU X1, X4", "MINPS X0, X4", "ORPS X4, X3", "MOVOU X3, X5", "CMPPS X5, X5, $3", "ORPS X5, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_mul": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MULPS X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_ne": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "CMPPS X1, X0, $4", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_nearest": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "ROUNDPS $0, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_neg": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstSign32(SB), X3", "XORPS X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_pmax": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "MAXPS X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_pmin": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "MINPS X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_replace_lane": {"MOVL X0, DI", "SHLL $5, CX", "MOVL CX, R13", "ANDL $63, CX", "MOVQ $4294967295, R10", "SHLQ CX, R10", "MOVQ DI, R11", "SHLQ CX, R11", "ANDQ R10, R11", "NOTQ R10", "MOVQ AX, AX", "MOVQ BX, BX", "MOVQ AX, R12", "ANDQ R10, R12", "ORQ R11, R12", "MOVQ BX, DX", "ANDQ R10, DX", "ORQ R11, DX", "TESTL $64, R13", "CMOVQEQ R12, AX", "CMOVQNE DX, BX"},
"f32x4_splat": {"SHUFPS $0, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_sqrt": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "SQRTPS X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_sub": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "SUBPS X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f32x4_trunc": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "ROUNDPS $3, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_abs": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstAbs64(SB), X3", "ANDPD X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_add": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "ADDPD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_ceil": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "ROUNDPD $2, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_convert_low_i32x4_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "CVTPL2PD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_convert_low_i32x4_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstMagicHi(SB), X3", "PUNPCKLLQ X3, X0", "MOVOU ·simdConstMagicd(SB), X4", "SUBPD X4, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_div": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "DIVPD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_eq": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "CMPPD X1, X0, $0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_extract_lane": {"MOVQ AX, R10", "TESTL $1, CX", "CMOVQNE BX, R10", "MOVQ R10, X0"},
"f64x2_floor": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "ROUNDPD $1, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_ge": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "CMPPD X0, X3, $2", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_gt": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "CMPPD X0, X3, $1", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_le": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "CMPPD X1, X0, $2", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_lt": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "CMPPD X1, X0, $1", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_max": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "MAXPD X1, X3", "MOVOU X1, X4", "MAXPD X0, X4", "MOVOU X3, X5", "XORPD X4, X5", "ORPD X5, X3", "SUBPD X5, X3", "MOVOU X3, X5", "CMPPD X5, X5, $3", "ORPD X5, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_min": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "MINPD X1, X3", "MOVOU X1, X4", "MINPD X0, X4", "ORPD X4, X3", "MOVOU X3, X5", "CMPPD X5, X5, $3", "ORPD X5, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_mul": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MULPD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_ne": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "CMPPD X1, X0, $4", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_nearest": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "ROUNDPD $0, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_neg": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstSign64(SB), X3", "XORPD X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_pmax": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "MAXPD X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_pmin": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "MINPD X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_promote_low_f32x4": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "CVTPS2PD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_replace_lane": {"MOVQ X0, DI", "MOVQ AX, AX", "MOVQ BX, BX", "TESTL $1, CX", "CMOVQEQ DI, AX", "CMOVQNE DI, BX"},
"f64x2_splat": {"UNPCKLPD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_sqrt": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "SQRTPD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_sub": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "SUBPD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"f64x2_trunc": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "ROUNDPD $3, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_abs": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PABSW X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_add": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PADDW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_add_sat_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PADDSW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_add_sat_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PADDUSW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_all_true": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PCMPEQW X0, X3", "PMOVMSKB X3, AX", "TESTL AX, AX", "SETEQ AX", "MOVBLZX AX, AX"},
"i16x8_avgr_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PAVGW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_bitmask": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PACKSSWB X0, X0", "PMOVMSKB X0, AX", "ANDL $0xff, AX"},
"i16x8_eq": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPEQW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extadd_pairwise_i8x16_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstOnes8(SB), X3", "PMADDUBSW X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extadd_pairwise_i8x16_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstOnes8(SB), X3", "PMADDUBSW X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extend_high_i8x16_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PSRLO $8, X0", "PMOVSXBW X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extend_high_i8x16_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PSRLO $8, X0", "PMOVZXBW X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extend_low_i8x16_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PMOVSXBW X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extend_low_i8x16_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PMOVZXBW X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extmul_high_i8x16_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSRLO $8, X0", "PSRLO $8, X1", "PMOVSXBW X0, X0", "PMOVSXBW X1, X1", "PMULLW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extmul_high_i8x16_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSRLO $8, X0", "PSRLO $8, X1", "PMOVZXBW X0, X0", "PMOVZXBW X1, X1", "PMULLW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extmul_low_i8x16_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMOVSXBW X0, X0", "PMOVSXBW X1, X1", "PMULLW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extmul_low_i8x16_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMOVZXBW X0, X0", "PMOVZXBW X1, X1", "PMULLW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_extract_lane_s": {"SHLL $4, CX", "MOVQ AX, R10", "TESTL $64, CX", "CMOVQNE BX, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVWQSX R10, AX"},
"i16x8_extract_lane_u": {"SHLL $4, CX", "MOVQ AX, R10", "TESTL $64, CX", "CMOVQNE BX, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVWQZX R10, AX"},
"i16x8_ge_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PCMPGTW X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_ge_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMAXUW X1, X3", "PCMPEQW X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_gt_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPGTW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_gt_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMINUW X1, X3", "PCMPEQW X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_le_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPGTW X1, X0", "PCMPEQL X4, X4", "PXOR X4, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_le_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMINUW X1, X3", "PCMPEQW X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_lt_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PCMPGTW X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_lt_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMAXUW X1, X3", "PCMPEQW X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_max_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMAXSW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_max_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMAXUW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_min_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMINSW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_min_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMINUW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_mul": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMULLW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_narrow_i32x4_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PACKSSLW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_narrow_i32x4_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PACKUSDW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_ne": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPEQW X1, X0", "PCMPEQL X3, X3", "PXOR X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_neg": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PSUBW X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_q15mulr_sat_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU ·simdConstI16Min(SB), X3", "MOVOU X0, X4", "PCMPEQW X3, X4", "MOVOU X1, X5", "PCMPEQW X3, X5", "PAND X5, X4", "PMULHRSW X1, X0", "PXOR X4, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_replace_lane": {"SHLL $4, CX", "MOVL CX, R13", "ANDL $63, CX", "MOVQ $65535, R10", "SHLQ CX, R10", "MOVQ DI, R11", "SHLQ CX, R11", "ANDQ R10, R11", "NOTQ R10", "MOVQ AX, AX", "MOVQ BX, BX", "MOVQ AX, R12", "ANDQ R10, R12", "ORQ R11, R12", "MOVQ BX, DX", "ANDQ R10, DX", "ORQ R11, DX", "TESTL $64, R13", "CMOVQEQ R12, AX", "CMOVQNE DX, BX"},
"i16x8_shl": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $15, AX", "MOVQ AX, X3", "PSLLW X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_shr_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $15, AX", "MOVQ AX, X3", "PSRAW X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_shr_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $15, AX", "MOVQ AX, X3", "PSRLW X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_splat": {"MOVQ AX, X0", "PSHUFLW $0, X0, X0", "PSHUFD $0, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_sub": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSUBW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_sub_sat_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSUBSW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i16x8_sub_sat_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSUBUSW X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_abs": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PABSD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_add": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PADDL X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_all_true": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PCMPEQL X0, X3", "PMOVMSKB X3, AX", "TESTL AX, AX", "SETEQ AX", "MOVBLZX AX, AX"},
"i32x4_bitmask": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVMSKPS X0, AX"},
"i32x4_dot_i16x8_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMADDWL X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_eq": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPEQL X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extadd_pairwise_i16x8_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstOnes16(SB), X3", "PMADDWL X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extadd_pairwise_i16x8_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU X0, X3", "PSRLL $16, X3", "PSLLL $16, X0", "PSRLL $16, X0", "PADDD X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extend_high_i16x8_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PSRLO $8, X0", "PMOVSXWD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extend_high_i16x8_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PSRLO $8, X0", "PMOVZXWD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extend_low_i16x8_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PMOVSXWD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extend_low_i16x8_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PMOVZXWD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extmul_high_i16x8_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSRLO $8, X0", "PSRLO $8, X1", "PMOVSXWD X0, X0", "PMOVSXWD X1, X1", "PMULLD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extmul_high_i16x8_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSRLO $8, X0", "PSRLO $8, X1", "PMOVZXWD X0, X0", "PMOVZXWD X1, X1", "PMULLD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extmul_low_i16x8_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMOVSXWD X0, X0", "PMOVSXWD X1, X1", "PMULLD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extmul_low_i16x8_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMOVZXWD X0, X0", "PMOVZXWD X1, X1", "PMULLD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_extract_lane": {"SHLL $5, CX", "MOVQ AX, R10", "TESTL $64, CX", "CMOVQNE BX, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVL R10, AX"},
"i32x4_ge_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PCMPGTL X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_ge_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMAXUD X1, X3", "PCMPEQL X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_gt_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPGTL X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_gt_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMINUD X1, X3", "PCMPEQL X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_le_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPGTL X1, X0", "PCMPEQL X4, X4", "PXOR X4, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_le_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMINUD X1, X3", "PCMPEQL X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_lt_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PCMPGTL X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_lt_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMAXUD X1, X3", "PCMPEQL X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_max_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMAXSD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_max_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMAXUD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_min_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMINSD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_min_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMINUD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_mul": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMULLD X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_ne": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPEQL X1, X0", "PCMPEQL X3, X3", "PXOR X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_neg": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PSUBL X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_replace_lane": {"SHLL $5, CX", "MOVL CX, R13", "ANDL $63, CX", "MOVQ $4294967295, R10", "SHLQ CX, R10", "MOVQ DI, R11", "SHLQ CX, R11", "ANDQ R10, R11", "NOTQ R10", "MOVQ AX, AX", "MOVQ BX, BX", "MOVQ AX, R12", "ANDQ R10, R12", "ORQ R11, R12", "MOVQ BX, DX", "ANDQ R10, DX", "ORQ R11, DX", "TESTL $64, R13", "CMOVQEQ R12, AX", "CMOVQNE DX, BX"},
"i32x4_shl": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $31, AX", "MOVQ AX, X3", "PSLLL X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_shr_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $31, AX", "MOVQ AX, X3", "PSRAL X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_shr_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $31, AX", "MOVQ AX, X3", "PSRLL X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_splat": {"MOVQ AX, X0", "PSHUFD $0, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_sub": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSUBL X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_trunc_sat_f32x4_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU X0, X3", "CMPPS X3, X3, $7", "ANDPS X3, X0", "MOVOU ·simdConst2p31f(SB), X4", "MOVOU X0, X5", "CMPPS X4, X5, $5", "CVTTPS2PL X0, X0", "PXOR X5, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_trunc_sat_f32x4_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "MAXPS X3, X0", "MOVOU ·simdConst2p31f(SB), X4", "MOVOU X0, X5", "SUBPS X4, X5", "MOVOU X5, X6", "CMPPS X4, X6, $5", "CVTTPS2PL X5, X5", "PXOR X6, X5", "PXOR X7, X7", "PMAXSD X7, X5", "CVTTPS2PL X0, X0", "PADDD X5, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_trunc_sat_f64x2_s_zero": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU X0, X3", "CMPPD X3, X3, $7", "ANDPD X3, X0", "MOVOU ·simdConst2p31d(SB), X4", "MINPD X4, X0", "CVTTPD2PL X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i32x4_trunc_sat_f64x2_u_zero": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "MAXPD X3, X0", "MOVOU ·simdConstUMaxd(SB), X4", "MINPD X4, X0", "ROUNDPD $3, X0, X0", "MOVOU ·simdConstMagicd(SB), X4", "ADDPD X4, X0", "SHUFPS $0x88, X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_abs": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PCMPGTQ X0, X3", "PXOR X3, X0", "PSUBQ X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_add": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PADDQ X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_all_true": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PCMPEQQ X0, X3", "PMOVMSKB X3, AX", "TESTL AX, AX", "SETEQ AX", "MOVBLZX AX, AX"},
"i64x2_bitmask": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVMSKPD X0, AX"},
"i64x2_eq": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPEQQ X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extend_high_i32x4_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PSRLO $8, X0", "PMOVSXDQ X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extend_high_i32x4_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PSRLO $8, X0", "PMOVZXDQ X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extend_low_i32x4_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PMOVSXDQ X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extend_low_i32x4_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PMOVZXDQ X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extmul_high_i32x4_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSHUFD $0xfa, X0, X0", "PSHUFD $0xfa, X1, X1", "PMULDQ X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extmul_high_i32x4_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSHUFD $0xfa, X0, X0", "PSHUFD $0xfa, X1, X1", "PMULULQ X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extmul_low_i32x4_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSHUFD $0x50, X0, X0", "PSHUFD $0x50, X1, X1", "PMULDQ X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extmul_low_i32x4_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSHUFD $0x50, X0, X0", "PSHUFD $0x50, X1, X1", "PMULULQ X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_extract_lane": {"MOVQ AX, R10", "TESTL $1, CX", "CMOVQNE BX, R10", "MOVQ R10, AX"},
"i64x2_ge_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PCMPGTQ X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_gt_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPGTQ X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_le_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPGTQ X1, X0", "PCMPEQL X4, X4", "PXOR X4, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_lt_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PCMPGTQ X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_ne": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPEQQ X1, X0", "PCMPEQL X3, X3", "PXOR X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_neg": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PSUBQ X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_replace_lane": {"MOVQ AX, AX", "MOVQ BX, BX", "TESTL $1, CX", "CMOVQEQ DI, AX", "CMOVQNE DI, BX"},
"i64x2_shl": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $63, AX", "MOVQ AX, X3", "PSLLQ X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_shr_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $63, AX", "MOVQ AX, X3", "PSRLQ X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_splat": {"MOVQ AX, X0", "PSHUFD $0x44, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i64x2_sub": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSUBQ X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_abs": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PABSB X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_add": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PADDB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_add_sat_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PADDSB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_add_sat_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PADDUSB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_all_true": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PCMPEQB X0, X3", "PMOVMSKB X3, AX", "TESTL AX, AX", "SETEQ AX", "MOVBLZX AX, AX"},
"i8x16_avgr_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PAVGB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_bitmask": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PMOVMSKB X0, AX"},
"i8x16_eq": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPEQB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_extract_lane_s": {"SHLL $3, CX", "MOVQ AX, R10", "TESTL $64, CX", "CMOVQNE BX, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVBQSX R10, AX"},
"i8x16_extract_lane_u": {"SHLL $3, CX", "MOVQ AX, R10", "TESTL $64, CX", "CMOVQNE BX, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVBQZX R10, AX"},
"i8x16_ge_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PCMPGTB X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_ge_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMAXUB X1, X3", "PCMPEQB X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_gt_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPGTB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_gt_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMINUB X1, X3", "PCMPEQB X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_le_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPGTB X1, X0", "PCMPEQL X4, X4", "PXOR X4, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_le_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMINUB X1, X3", "PCMPEQB X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_lt_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PCMPGTB X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_lt_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X0, X3", "PMAXUB X1, X3", "PCMPEQB X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_max_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMAXSB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_max_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMAXUB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_min_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMINSB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_min_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PMINUB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_narrow_i16x8_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PACKSSWB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_narrow_i16x8_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PACKUSWB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_ne": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PCMPEQB X1, X0", "PCMPEQL X3, X3", "PXOR X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_neg": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PSUBB X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_popcnt": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVOU ·simdConstPopLUT(SB), X3", "MOVOU ·simdConstNib(SB), X4", "MOVOU X0, X5", "PAND X4, X0", "PSRLW $4, X5", "PAND X4, X5", "MOVOU X3, X6", "PSHUFB X0, X6", "PSHUFB X5, X3", "PADDB X6, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_replace_lane": {"SHLL $3, CX", "MOVL CX, R13", "ANDL $63, CX", "MOVQ $255, R10", "SHLQ CX, R10", "MOVQ DI, R11", "SHLQ CX, R11", "ANDQ R10, R11", "NOTQ R10", "MOVQ AX, AX", "MOVQ BX, BX", "MOVQ AX, R12", "ANDQ R10, R12", "ORQ R11, R12", "MOVQ BX, DX", "ANDQ R10, DX", "ORQ R11, DX", "TESTL $64, R13", "CMOVQEQ R12, AX", "CMOVQNE DX, BX"},
"i8x16_shl": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $7, AX", "MOVQ AX, X3", "MOVL AX, CX", "MOVL $0xff, AX", "SHLL CX, AX", "ANDL $0xff, AX", "IMULL $0x01010101, AX", "MOVQ AX, X4", "PSHUFD $0, X4, X4", "PSLLW X3, X0", "PAND X4, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_shr_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $7, AX", "ADDL $8, AX", "MOVQ AX, X3", "MOVOU X0, X5", "PUNPCKLBW X0, X0", "PSRAW X3, X0", "PUNPCKHBW X5, X5", "PSRAW X3, X5", "PACKSSWB X5, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_shr_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, AX", "ANDL $7, AX", "MOVQ AX, X3", "MOVL AX, CX", "MOVL $0xff, AX", "SHRL CX, AX", "IMULL $0x01010101, AX", "MOVQ AX, X4", "PSHUFD $0, X4, X4", "PSRLW X3, X0", "PAND X4, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_shuffle": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVQ SI, X2", "PINSRQ $1, R8, X2", "MOVOU ·simdConst70(SB), X3", "MOVOU X2, X4", "PADDUSB X3, X4", "PSHUFB X4, X0", "MOVOU ·simdConst16(SB), X5", "PSUBB X5, X2", "PADDUSB X3, X2", "PSHUFB X2, X1", "POR X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_splat": {"MOVQ AX, X0", "PXOR X3, X3", "PSHUFB X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_sub": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSUBB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_sub_sat_s": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSUBSB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_sub_sat_u": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PSUBUSB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"i8x16_swizzle": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU ·simdConst70(SB), X3", "PADDUSB X3, X1", "PSHUFB X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"v128_and": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PAND X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"v128_andnot": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVOU X1, X3", "PANDN X0, X3", "MOVOU X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"v128_any_true": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PXOR X3, X3", "PCMPEQB X0, X3", "PMOVMSKB X3, AX", "CMPL AX, $0xffff", "SETNE AX", "MOVBLZX AX, AX"},
"v128_bitselect": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "MOVQ SI, X2", "PINSRQ $1, R8, X2", "PAND X2, X0", "PANDN X1, X2", "POR X2, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"v128_not": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "PCMPEQL X3, X3", "PXOR X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"v128_or": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "POR X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
"v128_xor": {"MOVQ AX, X0", "PINSRQ $1, BX, X0", "MOVQ CX, X1", "PINSRQ $1, DI, X1", "PXOR X1, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"},
}
// x64SimdPairMemSpliceTab: pair-form memory ops, amd64. Pre
// runs before the address preamble; Lines run with the checked
// host address in R11.
var x64SimdPairMemSpliceTab = map[string]struct {
Size int
Pre []string
Lines []string
}{
"v128_f16x4_cvt_store": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ DI, X0", "PINSRQ $1, SI, X0", "MOVOU X0, X1", "MOVQ $9223372034707292159, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PAND X4, X1", "MOVQ $-9223372034707292160, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PXOR X4, X1", "MOVQ $-36028792732385280, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PCMPGTL X4, X1", "MOVOU X0, X2", "PSRLL $16, X2", "MOVQ $140737488388096, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PAND X4, X2", "MOVOU X1, X3", "MOVQ $138538465132032, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PAND X4, X3", "POR X3, X2", "MOVOU X0, X3", "PSLLL $1, X3", "MOVQ $-72057589759737856, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PAND X4, X3", "MOVQ $8142508128181682176, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PMAXUD X4, X3", "PSRLL $1, X3", "MOVQ $540431955410288640, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PADDL X4, X3", "MOVQ $9223372034707292159, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PAND X4, X0", "MOVQ $8610882489537265664, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "MULPS X4, X0", "MOVQ $612489549464993792, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "MULPS X4, X0", "ADDPS X3, X0", "MOVOU X0, X3", "PSRLL $13, X3", "MOVQ $136339441875968, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PAND X4, X3", "MOVQ $17587891081215, AX", "MOVQ AX, X4", "PSHUFD $0x44, X4, X4", "PAND X4, X0", "PADDL X0, X3", "PANDN X3, X1", "POR X1, X2", "PACKUSDW X2, X2", "MOVQ X2, (R11)"}},
"v128_load": {Size: 16, Pre: []string{}, Lines: []string{"MOVQ (R11), AX", "MOVQ 8(R11), BX"}},
"v128_load16_lane": {Size: 2, Pre: []string{}, Lines: []string{"MOVWLZX (R11), R9", "MOVQ DI, CX", "SHLL $4, CX", "MOVL CX, R13", "ANDL $63, CX", "MOVQ $65535, R10", "SHLQ CX, R10", "MOVQ R9, R11", "SHLQ CX, R11", "ANDQ R10, R11", "NOTQ R10", "MOVQ SI, AX", "MOVQ R8, BX", "MOVQ AX, R12", "ANDQ R10, R12", "ORQ R11, R12", "MOVQ BX, DX", "ANDQ R10, DX", "ORQ R11, DX", "TESTL $64, R13", "CMOVQEQ R12, AX", "CMOVQNE DX, BX"}},
"v128_load16_splat": {Size: 2, Pre: []string{}, Lines: []string{"MOVWLZX (R11), AX", "MOVQ AX, X0", "PSHUFLW $0, X0, X0", "PSHUFD $0, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load16x4_s": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), X0", "PMOVSXWD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load16x4_u": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), X0", "PMOVZXWD X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load32_lane": {Size: 4, Pre: []string{}, Lines: []string{"MOVL (R11), R9", "MOVQ DI, CX", "SHLL $5, CX", "MOVL CX, R13", "ANDL $63, CX", "MOVQ $4294967295, R10", "SHLQ CX, R10", "MOVQ R9, R11", "SHLQ CX, R11", "ANDQ R10, R11", "NOTQ R10", "MOVQ SI, AX", "MOVQ R8, BX", "MOVQ AX, R12", "ANDQ R10, R12", "ORQ R11, R12", "MOVQ BX, DX", "ANDQ R10, DX", "ORQ R11, DX", "TESTL $64, R13", "CMOVQEQ R12, AX", "CMOVQNE DX, BX"}},
"v128_load32_splat": {Size: 4, Pre: []string{}, Lines: []string{"MOVL (R11), AX", "MOVQ AX, X0", "PSHUFD $0, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load32_zero": {Size: 4, Pre: []string{}, Lines: []string{"MOVL (R11), AX", "XORQ BX, BX"}},
"v128_load32x2_s": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), X0", "PMOVSXDQ X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load32x2_u": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), X0", "PMOVZXDQ X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load64_lane": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), R9", "MOVQ DI, CX", "MOVQ SI, AX", "MOVQ R8, BX", "TESTL $1, CX", "CMOVQEQ R9, AX", "CMOVQNE R9, BX"}},
"v128_load64_splat": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), AX", "MOVQ AX, X0", "PSHUFD $0x44, X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load64_zero": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), AX", "XORQ BX, BX"}},
"v128_load8_lane": {Size: 1, Pre: []string{}, Lines: []string{"MOVBLZX (R11), R9", "MOVQ DI, CX", "SHLL $3, CX", "MOVL CX, R13", "ANDL $63, CX", "MOVQ $255, R10", "SHLQ CX, R10", "MOVQ R9, R11", "SHLQ CX, R11", "ANDQ R10, R11", "NOTQ R10", "MOVQ SI, AX", "MOVQ R8, BX", "MOVQ AX, R12", "ANDQ R10, R12", "ORQ R11, R12", "MOVQ BX, DX", "ANDQ R10, DX", "ORQ R11, DX", "TESTL $64, R13", "CMOVQEQ R12, AX", "CMOVQNE DX, BX"}},
"v128_load8_splat": {Size: 1, Pre: []string{}, Lines: []string{"MOVBLZX (R11), AX", "MOVQ AX, X0", "PXOR X3, X3", "PSHUFB X3, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load8x8_s": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), X0", "PMOVSXBW X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_load8x8_u": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ (R11), X0", "PMOVZXBW X0, X0", "PEXTRQ $1, X0, BX", "MOVQ X0, AX"}},
"v128_store": {Size: 16, Pre: []string{}, Lines: []string{"MOVQ DI, (R11)", "MOVQ SI, 8(R11)"}},
"v128_store16_lane": {Size: 2, Pre: []string{}, Lines: []string{"MOVQ DI, CX", "SHLL $4, CX", "MOVQ SI, R10", "TESTL $64, CX", "CMOVQNE R8, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVW R10, (R11)"}},
"v128_store32_lane": {Size: 4, Pre: []string{}, Lines: []string{"MOVQ DI, CX", "SHLL $5, CX", "MOVQ SI, R10", "TESTL $64, CX", "CMOVQNE R8, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVL R10, (R11)"}},
"v128_store64_lane": {Size: 8, Pre: []string{}, Lines: []string{"MOVQ SI, R10", "TESTL $1, DI", "CMOVQNE R8, R10", "MOVQ R10, (R11)"}},
"v128_store8_lane": {Size: 1, Pre: []string{}, Lines: []string{"MOVQ DI, CX", "SHLL $3, CX", "MOVQ SI, R10", "TESTL $64, CX", "CMOVQNE R8, R10", "ANDL $63, CX", "SHRQ CX, R10", "MOVB R10, (R11)"}},
}
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