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f30ec292fd
* Support the wasm SIMD proposal with native asm lowering (arm64/amd64) One revision spanning the SIMD (0xfd v128) proposal end to end: SSA representation, lowering, scalar reference helpers, and a gcasm asm backend that turns the hot paths into native SIMD — measured on a full llama.cpp build transpiled to pure Go, which this makes run at V8-class speed (prompt eval beats V8 on arm64). Frontend and SSA: - v128 values are [2]uint64 pairs in little-endian lane order; pure ops lower to CSE-able helper calls, memory ops keep statement order, v128.const/shuffle ride as [2]uint64 aux. The full scalar helper set is the reference semantics (saturation, NaN propagation, round-to-even, swizzle OOB, shift masking). - Exception handling lowers to plain branches instead of panic/recover — a check-and-branch after each may-raise call, a per-try dispatch block running the catch-clause chain — covering the C++-shaped patterns (multi-clause catch, delegate targets, rethrow depths) without runtime unwinding, so EH bodies stay eligible for the asm backend. This replaces the closure/recover lowering that #39 extended; its tests are retained unchanged. - Giant functions outline into tractable units (whole loops included, packed u64 boundaries for v128 values), keeping gc compile times and register pressure sane on llama.cpp-sized modules. gcasm backend: - SIMD helper calls splice inline as native NEON/SSE instead of marshalled calls; v128 SSA values travel register-to-register in pair form. Call-tree windows fuse into single splices with region invariant hoisting, bounds-check coalescing, store sinks and scalar-chain internalization; whole countdown loops fuse with an in-splice unroll lane. - Superinstruction selection inside fused regions: 8-bit dot patterns (SMULL+SADALP), SDOT for full 16-byte dots, FMUL by element, scale-lookup addressing, inlined integer division, the software fp32->fp16 idiom lowered to FCVT (both the table-gather and the packed store form), and ggml q8_0 row/column pairing via the traits nrows patch with an SMMLA 2x2 tile kernel. - Runtime CPU-feature dispatch gates spliced bodies (dotprod on arm64, x86-64-v2 SSE on amd64); WASM2GO_FAST_MATH opts into raw-SDOT/FMLA/dual-accumulator forms that trade wasm bit-exactness for native-build-style rounding, validated by token-level equivalence against native llama.cpp. - Guard-page linear memory eliminates per-access bounds checks; jump tables replace the compare tree for br_table. Tooling and CI: - WASM2GO_F16_TABLE asserts the address of ggml's runtime-built f16 table; the transpiler warns when the asserted address matches no gather site (the address moves with every data-layout shift, and a stale assertion silently costs ~7% decode throughput). - The coverage gate runs with -count=1: a cached package result merges incomplete coverage data into the -coverpkg profile, deflating the total by 10+ points depending on what the runner's restored cache contained — the gate must never consume cached results. - Coverage threshold moves to 83% for the enlarged tree; transpile output is deterministic and outline rejections are explained in the build log. Co-Authored-By: Claude Fable 5 <[email protected]> * Replace environment-variable switches with typed Options; drop debug code Configuration now flows through one channel: transpile.Options gains OutlineMinValues, SIMDUnroll, FuseLoops, FuseLoopUnroll, F16TableAddr and FastMath (with matching CLI flags), the gcasm backend receives them as a Config threaded through ModuleOffsets, and no code path branches on an environment variable anymore. Integrator entry points (the wasmify protoc plugin, the CLI) convert their external configuration into these options exactly once. Deleted outright, per the no-env rule and because they were diagnostics rather than build modes: - every WASM2GO_NO_* kill switch and bisection knob (SSA pass disabling, fallback ranges, fuse-window caps, outline limits, inliner windows) — git history keeps them for the next hunt; - every env-gated debug printer (fuse/inline/outline/nrc2/f16/SSA dumps and the near-miss tracers) and the capture-tree keepers; - the dormant multi-exit loop structuring (opt-in, measured slower) and the SSA f32->f16 rewrite entry superseded by the gcasm peephole (its shared idiom matchers stay for the f16 store pass); - the runtime WASM2GO_CPU_PORTABLE override in the generated CPU feature probes. The nil-offsets error paths exposed by the threading get nil-safe Config accessors, and the outline share/v128-min/inliner caps become plain constants at their measured production values. Behavior under default options is unchanged: transpiled output for the non-SIMD and EH fixtures is byte-identical to the previous commit, and the only SIMD-bundle difference is the removed env check in the emitted cpufeat runtime files. Co-Authored-By: Claude Fable 5 <[email protected]> --------- Co-authored-by: Claude Fable 5 <[email protected]>
458 lines
35 KiB
Go
458 lines
35 KiB
Go
// Code generated by tools/gen-simd-asm/gen.py; DO NOT EDIT.
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package gcasm
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// a64SimdSpliceTab: op → arm64 body lines (WORD-encoded NEON plus
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// the occasional native line). See simdsplice_a64.go for how a
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// call site is rewritten around these.
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var a64SimdSpliceTab = map[string][]string{
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"f16x4_cvt_bits": {"WORD $0x0e216801 // fcvtn v1.4h, v0.4s", "WORD $0x4e20e402 // fcmeq v2.4s, v0.4s, v0.4s", "WORD $0x6f300403 // ushr v3.4s, v0.4s, #16", "WORD $0x4f042404 // movi v4.4s, #0x80, lsl #8", "WORD $0x4e241c63 // and v3.16b, v3.16b, v4.16b", "WORD $0x4f0327c4 // movi v4.4s, #0x7e, lsl #8", "WORD $0x4ea41c63 // orr v3.16b, v3.16b, v4.16b", "WORD $0x0e612842 // xtn v2.4h, v2.4s", "WORD $0x0e612863 // xtn v3.4h, v3.4s", "WORD $0x2e631c22 // bsl v2.8b, v1.8b, v3.8b", "FMOVD F2, R0"},
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"f32x4_abs": {"WORD $0x4ea0f800 // fabs v0.4s, v0.4s"},
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"f32x4_add": {"WORD $0x4e21d400 // fadd v0.4s, v0.4s, v1.4s"},
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"f32x4_ceil": {"WORD $0x4ea18800 // frintp v0.4s, v0.4s"},
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"f32x4_convert_i32x4_s": {"WORD $0x4e21d800 // scvtf v0.4s, v0.4s"},
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"f32x4_convert_i32x4_u": {"WORD $0x6e21d800 // ucvtf v0.4s, v0.4s"},
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"f32x4_demote_f64x2_zero": {"WORD $0x0e616800 // fcvtn v0.2s, v0.2d"},
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"f32x4_div": {"WORD $0x6e21fc00 // fdiv v0.4s, v0.4s, v1.4s"},
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"f32x4_eq": {"WORD $0x4e21e400 // fcmeq v0.4s, v0.4s, v1.4s"},
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"f32x4_floor": {"WORD $0x4e219800 // frintm v0.4s, v0.4s"},
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"f32x4_ge": {"WORD $0x6e21e400 // fcmge v0.4s, v0.4s, v1.4s"},
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"f32x4_gt": {"WORD $0x6ea1e400 // fcmgt v0.4s, v0.4s, v1.4s"},
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"f32x4_le": {"WORD $0x6e20e420 // fcmge v0.4s, v1.4s, v0.4s"},
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"f32x4_lt": {"WORD $0x6ea0e420 // fcmgt v0.4s, v1.4s, v0.4s"},
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"f32x4_max": {"WORD $0x4e21f400 // fmax v0.4s, v0.4s, v1.4s"},
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"f32x4_min": {"WORD $0x4ea1f400 // fmin v0.4s, v0.4s, v1.4s"},
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"f32x4_mul": {"WORD $0x6e21dc00 // fmul v0.4s, v0.4s, v1.4s"},
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"f32x4_ne": {"WORD $0x4e21e400 // fcmeq v0.4s, v0.4s, v1.4s", "WORD $0x6e205800 // mvn v0.16b, v0.16b"},
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"f32x4_nearest": {"WORD $0x4e218800 // frintn v0.4s, v0.4s"},
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"f32x4_neg": {"WORD $0x6ea0f800 // fneg v0.4s, v0.4s"},
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"f32x4_pmax": {"WORD $0x6ea0e422 // fcmgt v2.4s, v1.4s, v0.4s", "WORD $0x6e601c22 // bsl v2.16b, v1.16b, v0.16b", "WORD $0x4ea21c40 // mov v0.16b, v2.16b"},
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"f32x4_pmin": {"WORD $0x6ea1e402 // fcmgt v2.4s, v0.4s, v1.4s", "WORD $0x6e601c22 // bsl v2.16b, v1.16b, v0.16b", "WORD $0x4ea21c40 // mov v0.16b, v2.16b"},
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"f32x4_splat": {"WORD $0x4e040400 // dup v0.4s, v0.s[0]"},
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"f32x4_sqrt": {"WORD $0x6ea1f800 // fsqrt v0.4s, v0.4s"},
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"f32x4_sub": {"WORD $0x4ea1d400 // fsub v0.4s, v0.4s, v1.4s"},
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"f32x4_trunc": {"WORD $0x4ea19800 // frintz v0.4s, v0.4s"},
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"f64x2_abs": {"WORD $0x4ee0f800 // fabs v0.2d, v0.2d"},
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"f64x2_add": {"WORD $0x4e61d400 // fadd v0.2d, v0.2d, v1.2d"},
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"f64x2_ceil": {"WORD $0x4ee18800 // frintp v0.2d, v0.2d"},
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"f64x2_convert_low_i32x4_s": {"WORD $0x0f20a400 // sshll v0.2d, v0.2s, #0", "WORD $0x4e61d800 // scvtf v0.2d, v0.2d"},
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"f64x2_convert_low_i32x4_u": {"WORD $0x2f20a400 // ushll v0.2d, v0.2s, #0", "WORD $0x6e61d800 // ucvtf v0.2d, v0.2d"},
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"f64x2_div": {"WORD $0x6e61fc00 // fdiv v0.2d, v0.2d, v1.2d"},
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"f64x2_eq": {"WORD $0x4e61e400 // fcmeq v0.2d, v0.2d, v1.2d"},
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"f64x2_floor": {"WORD $0x4e619800 // frintm v0.2d, v0.2d"},
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"f64x2_ge": {"WORD $0x6e61e400 // fcmge v0.2d, v0.2d, v1.2d"},
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"f64x2_gt": {"WORD $0x6ee1e400 // fcmgt v0.2d, v0.2d, v1.2d"},
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"f64x2_le": {"WORD $0x6e60e420 // fcmge v0.2d, v1.2d, v0.2d"},
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"f64x2_lt": {"WORD $0x6ee0e420 // fcmgt v0.2d, v1.2d, v0.2d"},
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"f64x2_max": {"WORD $0x4e61f400 // fmax v0.2d, v0.2d, v1.2d"},
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"f64x2_min": {"WORD $0x4ee1f400 // fmin v0.2d, v0.2d, v1.2d"},
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"f64x2_mul": {"WORD $0x6e61dc00 // fmul v0.2d, v0.2d, v1.2d"},
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"f64x2_ne": {"WORD $0x4e61e400 // fcmeq v0.2d, v0.2d, v1.2d", "WORD $0x6e205800 // mvn v0.16b, v0.16b"},
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"f64x2_nearest": {"WORD $0x4e618800 // frintn v0.2d, v0.2d"},
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"f64x2_neg": {"WORD $0x6ee0f800 // fneg v0.2d, v0.2d"},
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"f64x2_pmax": {"WORD $0x6ee0e422 // fcmgt v2.2d, v1.2d, v0.2d", "WORD $0x6e601c22 // bsl v2.16b, v1.16b, v0.16b", "WORD $0x4ea21c40 // mov v0.16b, v2.16b"},
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"f64x2_pmin": {"WORD $0x6ee1e402 // fcmgt v2.2d, v0.2d, v1.2d", "WORD $0x6e601c22 // bsl v2.16b, v1.16b, v0.16b", "WORD $0x4ea21c40 // mov v0.16b, v2.16b"},
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"f64x2_promote_low_f32x4": {"WORD $0x0e617800 // fcvtl v0.2d, v0.2s"},
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"f64x2_splat": {"WORD $0x4e080400 // dup v0.2d, v0.d[0]"},
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"f64x2_sqrt": {"WORD $0x6ee1f800 // fsqrt v0.2d, v0.2d"},
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"f64x2_sub": {"WORD $0x4ee1d400 // fsub v0.2d, v0.2d, v1.2d"},
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"f64x2_trunc": {"WORD $0x4ee19800 // frintz v0.2d, v0.2d"},
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"i16x8_abs": {"WORD $0x4e60b800 // abs v0.8h, v0.8h"},
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"i16x8_add": {"WORD $0x4e618400 // add v0.8h, v0.8h, v1.8h"},
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"i16x8_add_sat_s": {"WORD $0x4e610c00 // sqadd v0.8h, v0.8h, v1.8h"},
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"i16x8_add_sat_u": {"WORD $0x6e610c00 // uqadd v0.8h, v0.8h, v1.8h"},
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"i16x8_all_true": {"WORD $0x6e71a801 // uminv h1, v0.8h", "WORD $0x0e023c20 // umov w0, v1.h[0]", "WORD $0x7100001f // cmp w0, #0", "WORD $0x1a9f07e0 // cset w0, ne"},
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"i16x8_avgr_u": {"WORD $0x6e611400 // urhadd v0.8h, v0.8h, v1.8h"},
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"i16x8_bitmask": {"WORD $0x4f110401 // sshr v1.8h, v0.8h, #15", "MOVD $·simdConstBitpos16(SB), R4", "FMOVQ (R4), F2", "WORD $0x4e221c21 // and v1.16b, v1.16b, v2.16b", "WORD $0x4e71b821 // addv h1, v1.8h", "WORD $0x0e023c20 // umov w0, v1.h[0]"},
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"i16x8_eq": {"WORD $0x6e618c00 // cmeq v0.8h, v0.8h, v1.8h"},
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"i16x8_extadd_pairwise_i8x16_s": {"WORD $0x4e202800 // saddlp v0.8h, v0.16b"},
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"i16x8_extadd_pairwise_i8x16_u": {"WORD $0x6e202800 // uaddlp v0.8h, v0.16b"},
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"i16x8_extend_high_i8x16_s": {"WORD $0x4f08a400 // sshll2 v0.8h, v0.16b, #0"},
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"i16x8_extend_high_i8x16_u": {"WORD $0x6f08a400 // ushll2 v0.8h, v0.16b, #0"},
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"i16x8_extend_low_i8x16_s": {"WORD $0x0f08a400 // sshll v0.8h, v0.8b, #0"},
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"i16x8_extend_low_i8x16_u": {"WORD $0x2f08a400 // ushll v0.8h, v0.8b, #0"},
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"i16x8_extmul_high_i8x16_s": {"WORD $0x4e21c000 // smull2 v0.8h, v0.16b, v1.16b"},
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"i16x8_extmul_high_i8x16_u": {"WORD $0x6e21c000 // umull2 v0.8h, v0.16b, v1.16b"},
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"i16x8_extmul_low_i8x16_s": {"WORD $0x0e21c000 // smull v0.8h, v0.8b, v1.8b"},
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"i16x8_extmul_low_i8x16_u": {"WORD $0x2e21c000 // umull v0.8h, v0.8b, v1.8b"},
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"i16x8_ge_s": {"WORD $0x4e613c00 // cmge v0.8h, v0.8h, v1.8h"},
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"i16x8_ge_u": {"WORD $0x6e613c00 // cmhs v0.8h, v0.8h, v1.8h"},
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"i16x8_gt_s": {"WORD $0x4e613400 // cmgt v0.8h, v0.8h, v1.8h"},
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"i16x8_gt_u": {"WORD $0x6e613400 // cmhi v0.8h, v0.8h, v1.8h"},
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"i16x8_le_s": {"WORD $0x4e603c20 // cmge v0.8h, v1.8h, v0.8h"},
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"i16x8_le_u": {"WORD $0x6e603c20 // cmhs v0.8h, v1.8h, v0.8h"},
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"i16x8_lt_s": {"WORD $0x4e603420 // cmgt v0.8h, v1.8h, v0.8h"},
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"i16x8_lt_u": {"WORD $0x6e603420 // cmhi v0.8h, v1.8h, v0.8h"},
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"i16x8_max_s": {"WORD $0x4e616400 // smax v0.8h, v0.8h, v1.8h"},
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"i16x8_max_u": {"WORD $0x6e616400 // umax v0.8h, v0.8h, v1.8h"},
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"i16x8_min_s": {"WORD $0x4e616c00 // smin v0.8h, v0.8h, v1.8h"},
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"i16x8_min_u": {"WORD $0x6e616c00 // umin v0.8h, v0.8h, v1.8h"},
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"i16x8_mul": {"WORD $0x4e619c00 // mul v0.8h, v0.8h, v1.8h"},
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"i16x8_narrow_i32x4_s": {"WORD $0x0e614800 // sqxtn v0.4h, v0.4s", "WORD $0x4e614820 // sqxtn2 v0.8h, v1.4s"},
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"i16x8_narrow_i32x4_u": {"WORD $0x2e612800 // sqxtun v0.4h, v0.4s", "WORD $0x6e612820 // sqxtun2 v0.8h, v1.4s"},
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"i16x8_ne": {"WORD $0x6e618c00 // cmeq v0.8h, v0.8h, v1.8h", "WORD $0x6e205800 // mvn v0.16b, v0.16b"},
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"i16x8_neg": {"WORD $0x6e60b800 // neg v0.8h, v0.8h"},
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"i16x8_q15mulr_sat_s": {"WORD $0x6e61b400 // sqrdmulh v0.8h, v0.8h, v1.8h"},
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"i16x8_shl": {"WORD $0x12000c00 // and w0, w0, #15", "WORD $0x4e020c01 // dup v1.8h, w0", "WORD $0x6e614400 // ushl v0.8h, v0.8h, v1.8h"},
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"i16x8_shr_s": {"WORD $0x12000c00 // and w0, w0, #15", "WORD $0x4b0003e0 // neg w0, w0", "WORD $0x4e020c01 // dup v1.8h, w0", "WORD $0x4e614400 // sshl v0.8h, v0.8h, v1.8h"},
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"i16x8_shr_u": {"WORD $0x12000c00 // and w0, w0, #15", "WORD $0x4b0003e0 // neg w0, w0", "WORD $0x4e020c01 // dup v1.8h, w0", "WORD $0x6e614400 // ushl v0.8h, v0.8h, v1.8h"},
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"i16x8_splat": {"WORD $0x4e020c00 // dup v0.8h, w0"},
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"i16x8_sub": {"WORD $0x6e618400 // sub v0.8h, v0.8h, v1.8h"},
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"i16x8_sub_sat_s": {"WORD $0x4e612c00 // sqsub v0.8h, v0.8h, v1.8h"},
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"i16x8_sub_sat_u": {"WORD $0x6e612c00 // uqsub v0.8h, v0.8h, v1.8h"},
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"i32x4_abs": {"WORD $0x4ea0b800 // abs v0.4s, v0.4s"},
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"i32x4_add": {"WORD $0x4ea18400 // add v0.4s, v0.4s, v1.4s"},
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"i32x4_all_true": {"WORD $0x6eb1a801 // uminv s1, v0.4s", "WORD $0x0e043c20 // umov w0, v1.s[0]", "WORD $0x7100001f // cmp w0, #0", "WORD $0x1a9f07e0 // cset w0, ne"},
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"i32x4_bitmask": {"WORD $0x4f210401 // sshr v1.4s, v0.4s, #31", "MOVD $·simdConstBitpos32(SB), R4", "FMOVQ (R4), F2", "WORD $0x4e221c21 // and v1.16b, v1.16b, v2.16b", "WORD $0x4eb1b821 // addv s1, v1.4s", "WORD $0x0e043c20 // umov w0, v1.s[0]"},
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"i32x4_dot_i16x8_s": {"WORD $0x0e61c002 // smull v2.4s, v0.4h, v1.4h", "WORD $0x4e61c003 // smull2 v3.4s, v0.8h, v1.8h", "WORD $0x4ea3bc40 // addp v0.4s, v2.4s, v3.4s"},
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"i32x4_eq": {"WORD $0x6ea18c00 // cmeq v0.4s, v0.4s, v1.4s"},
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"i32x4_extadd_pairwise_i16x8_s": {"WORD $0x4e602800 // saddlp v0.4s, v0.8h"},
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"i32x4_extadd_pairwise_i16x8_u": {"WORD $0x6e602800 // uaddlp v0.4s, v0.8h"},
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"i32x4_extend_high_i16x8_s": {"WORD $0x4f10a400 // sshll2 v0.4s, v0.8h, #0"},
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"i32x4_extend_high_i16x8_u": {"WORD $0x6f10a400 // ushll2 v0.4s, v0.8h, #0"},
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"i32x4_extend_low_i16x8_s": {"WORD $0x0f10a400 // sshll v0.4s, v0.4h, #0"},
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"i32x4_extend_low_i16x8_u": {"WORD $0x2f10a400 // ushll v0.4s, v0.4h, #0"},
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"i32x4_extmul_high_i16x8_s": {"WORD $0x4e61c000 // smull2 v0.4s, v0.8h, v1.8h"},
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"i32x4_extmul_high_i16x8_u": {"WORD $0x6e61c000 // umull2 v0.4s, v0.8h, v1.8h"},
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"i32x4_extmul_low_i16x8_s": {"WORD $0x0e61c000 // smull v0.4s, v0.4h, v1.4h"},
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"i32x4_extmul_low_i16x8_u": {"WORD $0x2e61c000 // umull v0.4s, v0.4h, v1.4h"},
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"i32x4_ge_s": {"WORD $0x4ea13c00 // cmge v0.4s, v0.4s, v1.4s"},
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"i32x4_ge_u": {"WORD $0x6ea13c00 // cmhs v0.4s, v0.4s, v1.4s"},
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"i32x4_gt_s": {"WORD $0x4ea13400 // cmgt v0.4s, v0.4s, v1.4s"},
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"i32x4_gt_u": {"WORD $0x6ea13400 // cmhi v0.4s, v0.4s, v1.4s"},
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"i32x4_le_s": {"WORD $0x4ea03c20 // cmge v0.4s, v1.4s, v0.4s"},
|
|
"i32x4_le_u": {"WORD $0x6ea03c20 // cmhs v0.4s, v1.4s, v0.4s"},
|
|
"i32x4_lt_s": {"WORD $0x4ea03420 // cmgt v0.4s, v1.4s, v0.4s"},
|
|
"i32x4_lt_u": {"WORD $0x6ea03420 // cmhi v0.4s, v1.4s, v0.4s"},
|
|
"i32x4_max_s": {"WORD $0x4ea16400 // smax v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_max_u": {"WORD $0x6ea16400 // umax v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_min_s": {"WORD $0x4ea16c00 // smin v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_min_u": {"WORD $0x6ea16c00 // umin v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_mul": {"WORD $0x4ea19c00 // mul v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_ne": {"WORD $0x6ea18c00 // cmeq v0.4s, v0.4s, v1.4s", "WORD $0x6e205800 // mvn v0.16b, v0.16b"},
|
|
"i32x4_neg": {"WORD $0x6ea0b800 // neg v0.4s, v0.4s"},
|
|
"i32x4_shl": {"WORD $0x12001000 // and w0, w0, #31", "WORD $0x4e040c01 // dup v1.4s, w0", "WORD $0x6ea14400 // ushl v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_shr_s": {"WORD $0x12001000 // and w0, w0, #31", "WORD $0x4b0003e0 // neg w0, w0", "WORD $0x4e040c01 // dup v1.4s, w0", "WORD $0x4ea14400 // sshl v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_shr_u": {"WORD $0x12001000 // and w0, w0, #31", "WORD $0x4b0003e0 // neg w0, w0", "WORD $0x4e040c01 // dup v1.4s, w0", "WORD $0x6ea14400 // ushl v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_splat": {"WORD $0x4e040c00 // dup v0.4s, w0"},
|
|
"i32x4_sub": {"WORD $0x6ea18400 // sub v0.4s, v0.4s, v1.4s"},
|
|
"i32x4_trunc_sat_f32x4_s": {"WORD $0x4ea1b800 // fcvtzs v0.4s, v0.4s"},
|
|
"i32x4_trunc_sat_f32x4_u": {"WORD $0x6ea1b800 // fcvtzu v0.4s, v0.4s"},
|
|
"i32x4_trunc_sat_f64x2_s_zero": {"WORD $0x4ee1b800 // fcvtzs v0.2d, v0.2d", "WORD $0x0ea14800 // sqxtn v0.2s, v0.2d"},
|
|
"i32x4_trunc_sat_f64x2_u_zero": {"WORD $0x6ee1b800 // fcvtzu v0.2d, v0.2d", "WORD $0x2ea14800 // uqxtn v0.2s, v0.2d"},
|
|
"i64x2_abs": {"WORD $0x4ee0b800 // abs v0.2d, v0.2d"},
|
|
"i64x2_add": {"WORD $0x4ee18400 // add v0.2d, v0.2d, v1.2d"},
|
|
"i64x2_all_true": {"WORD $0x4ee09800 // cmeq v0.2d, v0.2d, #0", "WORD $0x6e205800 // mvn v0.16b, v0.16b", "WORD $0x6eb1a801 // uminv s1, v0.4s", "WORD $0x0e043c20 // umov w0, v1.s[0]", "WORD $0x7100001f // cmp w0, #0", "WORD $0x1a9f07e0 // cset w0, ne"},
|
|
"i64x2_bitmask": {"WORD $0x4e083c01 // umov x1, v0.d[0]", "WORD $0x4e183c02 // umov x2, v0.d[1]", "WORD $0xd37ffc21 // lsr x1, x1, #63", "WORD $0xd37ffc42 // lsr x2, x2, #63", "WORD $0x2a020420 // orr w0, w1, w2, lsl #1"},
|
|
"i64x2_eq": {"WORD $0x6ee18c00 // cmeq v0.2d, v0.2d, v1.2d"},
|
|
"i64x2_extend_high_i32x4_s": {"WORD $0x4f20a400 // sshll2 v0.2d, v0.4s, #0"},
|
|
"i64x2_extend_high_i32x4_u": {"WORD $0x6f20a400 // ushll2 v0.2d, v0.4s, #0"},
|
|
"i64x2_extend_low_i32x4_s": {"WORD $0x0f20a400 // sshll v0.2d, v0.2s, #0"},
|
|
"i64x2_extend_low_i32x4_u": {"WORD $0x2f20a400 // ushll v0.2d, v0.2s, #0"},
|
|
"i64x2_extmul_high_i32x4_s": {"WORD $0x4ea1c000 // smull2 v0.2d, v0.4s, v1.4s"},
|
|
"i64x2_extmul_high_i32x4_u": {"WORD $0x6ea1c000 // umull2 v0.2d, v0.4s, v1.4s"},
|
|
"i64x2_extmul_low_i32x4_s": {"WORD $0x0ea1c000 // smull v0.2d, v0.2s, v1.2s"},
|
|
"i64x2_extmul_low_i32x4_u": {"WORD $0x2ea1c000 // umull v0.2d, v0.2s, v1.2s"},
|
|
"i64x2_ge_s": {"WORD $0x4ee13c00 // cmge v0.2d, v0.2d, v1.2d"},
|
|
"i64x2_gt_s": {"WORD $0x4ee13400 // cmgt v0.2d, v0.2d, v1.2d"},
|
|
"i64x2_le_s": {"WORD $0x4ee03c20 // cmge v0.2d, v1.2d, v0.2d"},
|
|
"i64x2_lt_s": {"WORD $0x4ee03420 // cmgt v0.2d, v1.2d, v0.2d"},
|
|
"i64x2_ne": {"WORD $0x6ee18c00 // cmeq v0.2d, v0.2d, v1.2d", "WORD $0x6e205800 // mvn v0.16b, v0.16b"},
|
|
"i64x2_neg": {"WORD $0x6ee0b800 // neg v0.2d, v0.2d"},
|
|
"i64x2_shl": {"WORD $0x12001400 // and w0, w0, #63", "WORD $0x4e080c01 // dup v1.2d, x0", "WORD $0x6ee14400 // ushl v0.2d, v0.2d, v1.2d"},
|
|
"i64x2_shr_s": {"WORD $0x12001400 // and w0, w0, #63", "WORD $0x4b0003e0 // neg w0, w0", "WORD $0x4e080c01 // dup v1.2d, x0", "WORD $0x4ee14400 // sshl v0.2d, v0.2d, v1.2d"},
|
|
"i64x2_shr_u": {"WORD $0x12001400 // and w0, w0, #63", "WORD $0x4b0003e0 // neg w0, w0", "WORD $0x4e080c01 // dup v1.2d, x0", "WORD $0x6ee14400 // ushl v0.2d, v0.2d, v1.2d"},
|
|
"i64x2_splat": {"WORD $0x4e080c00 // dup v0.2d, x0"},
|
|
"i64x2_sub": {"WORD $0x6ee18400 // sub v0.2d, v0.2d, v1.2d"},
|
|
"i8x16_abs": {"WORD $0x4e20b800 // abs v0.16b, v0.16b"},
|
|
"i8x16_add": {"WORD $0x4e218400 // add v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_add_sat_s": {"WORD $0x4e210c00 // sqadd v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_add_sat_u": {"WORD $0x6e210c00 // uqadd v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_all_true": {"WORD $0x6e31a801 // uminv b1, v0.16b", "WORD $0x0e013c20 // umov w0, v1.b[0]", "WORD $0x7100001f // cmp w0, #0", "WORD $0x1a9f07e0 // cset w0, ne"},
|
|
"i8x16_avgr_u": {"WORD $0x6e211400 // urhadd v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_bitmask": {"WORD $0x4f090401 // sshr v1.16b, v0.16b, #7", "MOVD $·simdConstBitpos8(SB), R4", "FMOVQ (R4), F2", "WORD $0x4e221c21 // and v1.16b, v1.16b, v2.16b", "WORD $0x4e083c21 // umov x1, v1.d[0]", "WORD $0x4e183c22 // umov x2, v1.d[1]", "MOVD $0x0101010101010101, R3", "WORD $0x9b037c21 // mul x1, x1, x3", "WORD $0x9b037c42 // mul x2, x2, x3", "WORD $0xd378fc21 // lsr x1, x1, #56", "WORD $0xd378fc42 // lsr x2, x2, #56", "WORD $0x2a022020 // orr w0, w1, w2, lsl #8"},
|
|
"i8x16_eq": {"WORD $0x6e218c00 // cmeq v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_ge_s": {"WORD $0x4e213c00 // cmge v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_ge_u": {"WORD $0x6e213c00 // cmhs v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_gt_s": {"WORD $0x4e213400 // cmgt v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_gt_u": {"WORD $0x6e213400 // cmhi v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_le_s": {"WORD $0x4e203c20 // cmge v0.16b, v1.16b, v0.16b"},
|
|
"i8x16_le_u": {"WORD $0x6e203c20 // cmhs v0.16b, v1.16b, v0.16b"},
|
|
"i8x16_lt_s": {"WORD $0x4e203420 // cmgt v0.16b, v1.16b, v0.16b"},
|
|
"i8x16_lt_u": {"WORD $0x6e203420 // cmhi v0.16b, v1.16b, v0.16b"},
|
|
"i8x16_max_s": {"WORD $0x4e216400 // smax v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_max_u": {"WORD $0x6e216400 // umax v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_min_s": {"WORD $0x4e216c00 // smin v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_min_u": {"WORD $0x6e216c00 // umin v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_narrow_i16x8_s": {"WORD $0x0e214800 // sqxtn v0.8b, v0.8h", "WORD $0x4e214820 // sqxtn2 v0.16b, v1.8h"},
|
|
"i8x16_narrow_i16x8_u": {"WORD $0x2e212800 // sqxtun v0.8b, v0.8h", "WORD $0x6e212820 // sqxtun2 v0.16b, v1.8h"},
|
|
"i8x16_ne": {"WORD $0x6e218c00 // cmeq v0.16b, v0.16b, v1.16b", "WORD $0x6e205800 // mvn v0.16b, v0.16b"},
|
|
"i8x16_neg": {"WORD $0x6e20b800 // neg v0.16b, v0.16b"},
|
|
"i8x16_popcnt": {"WORD $0x4e205800 // cnt v0.16b, v0.16b"},
|
|
"i8x16_shl": {"WORD $0x12000800 // and w0, w0, #7", "WORD $0x4e010c01 // dup v1.16b, w0", "WORD $0x6e214400 // ushl v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_shr_s": {"WORD $0x12000800 // and w0, w0, #7", "WORD $0x4b0003e0 // neg w0, w0", "WORD $0x4e010c01 // dup v1.16b, w0", "WORD $0x4e214400 // sshl v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_shr_u": {"WORD $0x12000800 // and w0, w0, #7", "WORD $0x4b0003e0 // neg w0, w0", "WORD $0x4e010c01 // dup v1.16b, w0", "WORD $0x6e214400 // ushl v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_shuffle": {"WORD $0x4e022000 // tbl v0.16b, {v0.16b, v1.16b}, v2.16b"},
|
|
"i8x16_splat": {"WORD $0x4e010c00 // dup v0.16b, w0"},
|
|
"i8x16_sub": {"WORD $0x6e218400 // sub v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_sub_sat_s": {"WORD $0x4e212c00 // sqsub v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_sub_sat_u": {"WORD $0x6e212c00 // uqsub v0.16b, v0.16b, v1.16b"},
|
|
"i8x16_swizzle": {"WORD $0x4e010000 // tbl v0.16b, {v0.16b}, v1.16b"},
|
|
"v128_and": {"WORD $0x4e211c00 // and v0.16b, v0.16b, v1.16b"},
|
|
"v128_andnot": {"WORD $0x4e611c00 // bic v0.16b, v0.16b, v1.16b"},
|
|
"v128_any_true": {"WORD $0x6e30a801 // umaxv b1, v0.16b", "WORD $0x0e013c20 // umov w0, v1.b[0]", "WORD $0x7100001f // cmp w0, #0", "WORD $0x1a9f07e0 // cset w0, ne"},
|
|
"v128_bitselect": {"WORD $0x4ea21c43 // mov v3.16b, v2.16b", "WORD $0x6e611c03 // bsl v3.16b, v0.16b, v1.16b", "WORD $0x4ea31c60 // mov v0.16b, v3.16b"},
|
|
"v128_not": {"WORD $0x6e205800 // mvn v0.16b, v0.16b"},
|
|
"v128_or": {"WORD $0x4ea11c00 // orr v0.16b, v0.16b, v1.16b"},
|
|
"v128_xor": {"WORD $0x6e211c00 // eor v0.16b, v0.16b, v1.16b"},
|
|
}
|
|
|
|
// x64SimdSpliceTab: op → amd64 body lines (native Go asm, SSE,
|
|
// x86-64-v2 baseline — the same guard as the helper bodies).
|
|
var x64SimdSpliceTab = map[string][]string{
|
|
"f32x4_abs": {"MOVOU ·simdConstAbs32(SB), X3", "ANDPS X3, X0"},
|
|
"f32x4_add": {"ADDPS X1, X0"},
|
|
"f32x4_ceil": {"ROUNDPS $2, X0, X0"},
|
|
"f32x4_convert_i32x4_s": {"CVTPL2PS X0, X0"},
|
|
"f32x4_convert_i32x4_u": {"MOVOU X0, X3", "PSRLL $16, X3", "PSLLL $16, X0", "PSRLL $16, X0", "CVTPL2PS X0, X0", "CVTPL2PS X3, X3", "MOVOU ·simdConst65536f(SB), X4", "MULPS X4, X3", "ADDPS X3, X0"},
|
|
"f32x4_demote_f64x2_zero": {"CVTPD2PS X0, X0"},
|
|
"f32x4_div": {"DIVPS X1, X0"},
|
|
"f32x4_eq": {"CMPPS X1, X0, $0"},
|
|
"f32x4_floor": {"ROUNDPS $1, X0, X0"},
|
|
"f32x4_ge": {"MOVOU X1, X3", "CMPPS X0, X3, $2", "MOVOU X3, X0"},
|
|
"f32x4_gt": {"MOVOU X1, X3", "CMPPS X0, X3, $1", "MOVOU X3, X0"},
|
|
"f32x4_le": {"CMPPS X1, X0, $2"},
|
|
"f32x4_lt": {"CMPPS X1, X0, $1"},
|
|
"f32x4_max": {"MOVOU X0, X3", "MAXPS X1, X3", "MOVOU X1, X4", "MAXPS X0, X4", "MOVOU X3, X5", "XORPS X4, X5", "ORPS X5, X3", "SUBPS X5, X3", "MOVOU X3, X5", "CMPPS X5, X5, $3", "ORPS X5, X3", "MOVOU X3, X0"},
|
|
"f32x4_min": {"MOVOU X0, X3", "MINPS X1, X3", "MOVOU X1, X4", "MINPS X0, X4", "ORPS X4, X3", "MOVOU X3, X5", "CMPPS X5, X5, $3", "ORPS X5, X3", "MOVOU X3, X0"},
|
|
"f32x4_mul": {"MULPS X1, X0"},
|
|
"f32x4_ne": {"CMPPS X1, X0, $4"},
|
|
"f32x4_nearest": {"ROUNDPS $0, X0, X0"},
|
|
"f32x4_neg": {"MOVOU ·simdConstSign32(SB), X3", "XORPS X3, X0"},
|
|
"f32x4_pmax": {"MOVOU X1, X3", "MAXPS X0, X3", "MOVOU X3, X0"},
|
|
"f32x4_pmin": {"MOVOU X1, X3", "MINPS X0, X3", "MOVOU X3, X0"},
|
|
"f32x4_splat": {"SHUFPS $0, X0, X0"},
|
|
"f32x4_sqrt": {"SQRTPS X0, X0"},
|
|
"f32x4_sub": {"SUBPS X1, X0"},
|
|
"f32x4_trunc": {"ROUNDPS $3, X0, X0"},
|
|
"f64x2_abs": {"MOVOU ·simdConstAbs64(SB), X3", "ANDPD X3, X0"},
|
|
"f64x2_add": {"ADDPD X1, X0"},
|
|
"f64x2_ceil": {"ROUNDPD $2, X0, X0"},
|
|
"f64x2_convert_low_i32x4_s": {"CVTPL2PD X0, X0"},
|
|
"f64x2_convert_low_i32x4_u": {"MOVOU ·simdConstMagicHi(SB), X3", "PUNPCKLLQ X3, X0", "MOVOU ·simdConstMagicd(SB), X4", "SUBPD X4, X0"},
|
|
"f64x2_div": {"DIVPD X1, X0"},
|
|
"f64x2_eq": {"CMPPD X1, X0, $0"},
|
|
"f64x2_floor": {"ROUNDPD $1, X0, X0"},
|
|
"f64x2_ge": {"MOVOU X1, X3", "CMPPD X0, X3, $2", "MOVOU X3, X0"},
|
|
"f64x2_gt": {"MOVOU X1, X3", "CMPPD X0, X3, $1", "MOVOU X3, X0"},
|
|
"f64x2_le": {"CMPPD X1, X0, $2"},
|
|
"f64x2_lt": {"CMPPD X1, X0, $1"},
|
|
"f64x2_max": {"MOVOU X0, X3", "MAXPD X1, X3", "MOVOU X1, X4", "MAXPD X0, X4", "MOVOU X3, X5", "XORPD X4, X5", "ORPD X5, X3", "SUBPD X5, X3", "MOVOU X3, X5", "CMPPD X5, X5, $3", "ORPD X5, X3", "MOVOU X3, X0"},
|
|
"f64x2_min": {"MOVOU X0, X3", "MINPD X1, X3", "MOVOU X1, X4", "MINPD X0, X4", "ORPD X4, X3", "MOVOU X3, X5", "CMPPD X5, X5, $3", "ORPD X5, X3", "MOVOU X3, X0"},
|
|
"f64x2_mul": {"MULPD X1, X0"},
|
|
"f64x2_ne": {"CMPPD X1, X0, $4"},
|
|
"f64x2_nearest": {"ROUNDPD $0, X0, X0"},
|
|
"f64x2_neg": {"MOVOU ·simdConstSign64(SB), X3", "XORPD X3, X0"},
|
|
"f64x2_pmax": {"MOVOU X1, X3", "MAXPD X0, X3", "MOVOU X3, X0"},
|
|
"f64x2_pmin": {"MOVOU X1, X3", "MINPD X0, X3", "MOVOU X3, X0"},
|
|
"f64x2_promote_low_f32x4": {"CVTPS2PD X0, X0"},
|
|
"f64x2_splat": {"UNPCKLPD X0, X0"},
|
|
"f64x2_sqrt": {"SQRTPD X0, X0"},
|
|
"f64x2_sub": {"SUBPD X1, X0"},
|
|
"f64x2_trunc": {"ROUNDPD $3, X0, X0"},
|
|
"i16x8_abs": {"PABSW X0, X0"},
|
|
"i16x8_add": {"PADDW X1, X0"},
|
|
"i16x8_add_sat_s": {"PADDSW X1, X0"},
|
|
"i16x8_add_sat_u": {"PADDUSW X1, X0"},
|
|
"i16x8_all_true": {"PXOR X3, X3", "PCMPEQW X0, X3", "PMOVMSKB X3, AX", "TESTL AX, AX", "SETEQ AX", "MOVBLZX AX, AX"},
|
|
"i16x8_avgr_u": {"PAVGW X1, X0"},
|
|
"i16x8_bitmask": {"PACKSSWB X0, X0", "PMOVMSKB X0, AX", "ANDL $0xff, AX"},
|
|
"i16x8_eq": {"PCMPEQW X1, X0"},
|
|
"i16x8_extadd_pairwise_i8x16_s": {"MOVOU ·simdConstOnes8(SB), X3", "PMADDUBSW X0, X3", "MOVOU X3, X0"},
|
|
"i16x8_extadd_pairwise_i8x16_u": {"MOVOU ·simdConstOnes8(SB), X3", "PMADDUBSW X3, X0"},
|
|
"i16x8_extend_high_i8x16_s": {"PSRLO $8, X0", "PMOVSXBW X0, X0"},
|
|
"i16x8_extend_high_i8x16_u": {"PSRLO $8, X0", "PMOVZXBW X0, X0"},
|
|
"i16x8_extend_low_i8x16_s": {"PMOVSXBW X0, X0"},
|
|
"i16x8_extend_low_i8x16_u": {"PMOVZXBW X0, X0"},
|
|
"i16x8_extmul_high_i8x16_s": {"PSRLO $8, X0", "PSRLO $8, X1", "PMOVSXBW X0, X0", "PMOVSXBW X1, X1", "PMULLW X1, X0"},
|
|
"i16x8_extmul_high_i8x16_u": {"PSRLO $8, X0", "PSRLO $8, X1", "PMOVZXBW X0, X0", "PMOVZXBW X1, X1", "PMULLW X1, X0"},
|
|
"i16x8_extmul_low_i8x16_s": {"PMOVSXBW X0, X0", "PMOVSXBW X1, X1", "PMULLW X1, X0"},
|
|
"i16x8_extmul_low_i8x16_u": {"PMOVZXBW X0, X0", "PMOVZXBW X1, X1", "PMULLW X1, X0"},
|
|
"i16x8_ge_s": {"MOVOU X1, X3", "PCMPGTW X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i16x8_ge_u": {"MOVOU X0, X3", "PMAXUW X1, X3", "PCMPEQW X0, X3", "MOVOU X3, X0"},
|
|
"i16x8_gt_s": {"PCMPGTW X1, X0"},
|
|
"i16x8_gt_u": {"MOVOU X0, X3", "PMINUW X1, X3", "PCMPEQW X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i16x8_le_s": {"PCMPGTW X1, X0", "PCMPEQL X4, X4", "PXOR X4, X0"},
|
|
"i16x8_le_u": {"MOVOU X0, X3", "PMINUW X1, X3", "PCMPEQW X0, X3", "MOVOU X3, X0"},
|
|
"i16x8_lt_s": {"MOVOU X1, X3", "PCMPGTW X0, X3", "MOVOU X3, X0"},
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|
"i16x8_lt_u": {"MOVOU X0, X3", "PMAXUW X1, X3", "PCMPEQW X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
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|
"i16x8_max_s": {"PMAXSW X1, X0"},
|
|
"i16x8_max_u": {"PMAXUW X1, X0"},
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|
"i16x8_min_s": {"PMINSW X1, X0"},
|
|
"i16x8_min_u": {"PMINUW X1, X0"},
|
|
"i16x8_mul": {"PMULLW X1, X0"},
|
|
"i16x8_narrow_i32x4_s": {"PACKSSLW X1, X0"},
|
|
"i16x8_narrow_i32x4_u": {"PACKUSDW X1, X0"},
|
|
"i16x8_ne": {"PCMPEQW X1, X0", "PCMPEQL X3, X3", "PXOR X3, X0"},
|
|
"i16x8_neg": {"PXOR X3, X3", "PSUBW X0, X3", "MOVOU X3, X0"},
|
|
"i16x8_q15mulr_sat_s": {"MOVOU ·simdConstI16Min(SB), X3", "MOVOU X0, X4", "PCMPEQW X3, X4", "MOVOU X1, X5", "PCMPEQW X3, X5", "PAND X5, X4", "PMULHRSW X1, X0", "PXOR X4, X0"},
|
|
"i16x8_shl": {"ANDL $15, AX", "MOVQ AX, X3", "PSLLW X3, X0"},
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|
"i16x8_shr_s": {"ANDL $15, AX", "MOVQ AX, X3", "PSRAW X3, X0"},
|
|
"i16x8_shr_u": {"ANDL $15, AX", "MOVQ AX, X3", "PSRLW X3, X0"},
|
|
"i16x8_splat": {"MOVQ AX, X0", "PSHUFLW $0, X0, X0", "PSHUFD $0, X0, X0"},
|
|
"i16x8_sub": {"PSUBW X1, X0"},
|
|
"i16x8_sub_sat_s": {"PSUBSW X1, X0"},
|
|
"i16x8_sub_sat_u": {"PSUBUSW X1, X0"},
|
|
"i32x4_abs": {"PABSD X0, X0"},
|
|
"i32x4_add": {"PADDL X1, X0"},
|
|
"i32x4_all_true": {"PXOR X3, X3", "PCMPEQL X0, X3", "PMOVMSKB X3, AX", "TESTL AX, AX", "SETEQ AX", "MOVBLZX AX, AX"},
|
|
"i32x4_bitmask": {"MOVMSKPS X0, AX"},
|
|
"i32x4_dot_i16x8_s": {"PMADDWL X1, X0"},
|
|
"i32x4_eq": {"PCMPEQL X1, X0"},
|
|
"i32x4_extadd_pairwise_i16x8_s": {"MOVOU ·simdConstOnes16(SB), X3", "PMADDWL X3, X0"},
|
|
"i32x4_extadd_pairwise_i16x8_u": {"MOVOU X0, X3", "PSRLL $16, X3", "PSLLL $16, X0", "PSRLL $16, X0", "PADDD X3, X0"},
|
|
"i32x4_extend_high_i16x8_s": {"PSRLO $8, X0", "PMOVSXWD X0, X0"},
|
|
"i32x4_extend_high_i16x8_u": {"PSRLO $8, X0", "PMOVZXWD X0, X0"},
|
|
"i32x4_extend_low_i16x8_s": {"PMOVSXWD X0, X0"},
|
|
"i32x4_extend_low_i16x8_u": {"PMOVZXWD X0, X0"},
|
|
"i32x4_extmul_high_i16x8_s": {"PSRLO $8, X0", "PSRLO $8, X1", "PMOVSXWD X0, X0", "PMOVSXWD X1, X1", "PMULLD X1, X0"},
|
|
"i32x4_extmul_high_i16x8_u": {"PSRLO $8, X0", "PSRLO $8, X1", "PMOVZXWD X0, X0", "PMOVZXWD X1, X1", "PMULLD X1, X0"},
|
|
"i32x4_extmul_low_i16x8_s": {"PMOVSXWD X0, X0", "PMOVSXWD X1, X1", "PMULLD X1, X0"},
|
|
"i32x4_extmul_low_i16x8_u": {"PMOVZXWD X0, X0", "PMOVZXWD X1, X1", "PMULLD X1, X0"},
|
|
"i32x4_ge_s": {"MOVOU X1, X3", "PCMPGTL X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i32x4_ge_u": {"MOVOU X0, X3", "PMAXUD X1, X3", "PCMPEQL X0, X3", "MOVOU X3, X0"},
|
|
"i32x4_gt_s": {"PCMPGTL X1, X0"},
|
|
"i32x4_gt_u": {"MOVOU X0, X3", "PMINUD X1, X3", "PCMPEQL X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i32x4_le_s": {"PCMPGTL X1, X0", "PCMPEQL X4, X4", "PXOR X4, X0"},
|
|
"i32x4_le_u": {"MOVOU X0, X3", "PMINUD X1, X3", "PCMPEQL X0, X3", "MOVOU X3, X0"},
|
|
"i32x4_lt_s": {"MOVOU X1, X3", "PCMPGTL X0, X3", "MOVOU X3, X0"},
|
|
"i32x4_lt_u": {"MOVOU X0, X3", "PMAXUD X1, X3", "PCMPEQL X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i32x4_max_s": {"PMAXSD X1, X0"},
|
|
"i32x4_max_u": {"PMAXUD X1, X0"},
|
|
"i32x4_min_s": {"PMINSD X1, X0"},
|
|
"i32x4_min_u": {"PMINUD X1, X0"},
|
|
"i32x4_mul": {"PMULLD X1, X0"},
|
|
"i32x4_ne": {"PCMPEQL X1, X0", "PCMPEQL X3, X3", "PXOR X3, X0"},
|
|
"i32x4_neg": {"PXOR X3, X3", "PSUBL X0, X3", "MOVOU X3, X0"},
|
|
"i32x4_shl": {"ANDL $31, AX", "MOVQ AX, X3", "PSLLL X3, X0"},
|
|
"i32x4_shr_s": {"ANDL $31, AX", "MOVQ AX, X3", "PSRAL X3, X0"},
|
|
"i32x4_shr_u": {"ANDL $31, AX", "MOVQ AX, X3", "PSRLL X3, X0"},
|
|
"i32x4_splat": {"MOVQ AX, X0", "PSHUFD $0, X0, X0"},
|
|
"i32x4_sub": {"PSUBL X1, X0"},
|
|
"i32x4_trunc_sat_f32x4_s": {"MOVOU X0, X3", "CMPPS X3, X3, $7", "ANDPS X3, X0", "MOVOU ·simdConst2p31f(SB), X4", "MOVOU X0, X5", "CMPPS X4, X5, $5", "CVTTPS2PL X0, X0", "PXOR X5, X0"},
|
|
"i32x4_trunc_sat_f32x4_u": {"PXOR X3, X3", "MAXPS X3, X0", "MOVOU ·simdConst2p31f(SB), X4", "MOVOU X0, X5", "SUBPS X4, X5", "MOVOU X5, X6", "CMPPS X4, X6, $5", "CVTTPS2PL X5, X5", "PXOR X6, X5", "PXOR X7, X7", "PMAXSD X7, X5", "CVTTPS2PL X0, X0", "PADDD X5, X0"},
|
|
"i32x4_trunc_sat_f64x2_s_zero": {"MOVOU X0, X3", "CMPPD X3, X3, $7", "ANDPD X3, X0", "MOVOU ·simdConst2p31d(SB), X4", "MINPD X4, X0", "CVTTPD2PL X0, X0"},
|
|
"i32x4_trunc_sat_f64x2_u_zero": {"PXOR X3, X3", "MAXPD X3, X0", "MOVOU ·simdConstUMaxd(SB), X4", "MINPD X4, X0", "ROUNDPD $3, X0, X0", "MOVOU ·simdConstMagicd(SB), X4", "ADDPD X4, X0", "SHUFPS $0x88, X3, X0"},
|
|
"i64x2_abs": {"PXOR X3, X3", "PCMPGTQ X0, X3", "PXOR X3, X0", "PSUBQ X3, X0"},
|
|
"i64x2_add": {"PADDQ X1, X0"},
|
|
"i64x2_all_true": {"PXOR X3, X3", "PCMPEQQ X0, X3", "PMOVMSKB X3, AX", "TESTL AX, AX", "SETEQ AX", "MOVBLZX AX, AX"},
|
|
"i64x2_bitmask": {"MOVMSKPD X0, AX"},
|
|
"i64x2_eq": {"PCMPEQQ X1, X0"},
|
|
"i64x2_extend_high_i32x4_s": {"PSRLO $8, X0", "PMOVSXDQ X0, X0"},
|
|
"i64x2_extend_high_i32x4_u": {"PSRLO $8, X0", "PMOVZXDQ X0, X0"},
|
|
"i64x2_extend_low_i32x4_s": {"PMOVSXDQ X0, X0"},
|
|
"i64x2_extend_low_i32x4_u": {"PMOVZXDQ X0, X0"},
|
|
"i64x2_extmul_high_i32x4_s": {"PSHUFD $0xfa, X0, X0", "PSHUFD $0xfa, X1, X1", "PMULDQ X1, X0"},
|
|
"i64x2_extmul_high_i32x4_u": {"PSHUFD $0xfa, X0, X0", "PSHUFD $0xfa, X1, X1", "PMULULQ X1, X0"},
|
|
"i64x2_extmul_low_i32x4_s": {"PSHUFD $0x50, X0, X0", "PSHUFD $0x50, X1, X1", "PMULDQ X1, X0"},
|
|
"i64x2_extmul_low_i32x4_u": {"PSHUFD $0x50, X0, X0", "PSHUFD $0x50, X1, X1", "PMULULQ X1, X0"},
|
|
"i64x2_ge_s": {"MOVOU X1, X3", "PCMPGTQ X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i64x2_gt_s": {"PCMPGTQ X1, X0"},
|
|
"i64x2_le_s": {"PCMPGTQ X1, X0", "PCMPEQL X4, X4", "PXOR X4, X0"},
|
|
"i64x2_lt_s": {"MOVOU X1, X3", "PCMPGTQ X0, X3", "MOVOU X3, X0"},
|
|
"i64x2_ne": {"PCMPEQQ X1, X0", "PCMPEQL X3, X3", "PXOR X3, X0"},
|
|
"i64x2_neg": {"PXOR X3, X3", "PSUBQ X0, X3", "MOVOU X3, X0"},
|
|
"i64x2_shl": {"ANDL $63, AX", "MOVQ AX, X3", "PSLLQ X3, X0"},
|
|
"i64x2_shr_u": {"ANDL $63, AX", "MOVQ AX, X3", "PSRLQ X3, X0"},
|
|
"i64x2_splat": {"MOVQ AX, X0", "PSHUFD $0x44, X0, X0"},
|
|
"i64x2_sub": {"PSUBQ X1, X0"},
|
|
"i8x16_abs": {"PABSB X0, X0"},
|
|
"i8x16_add": {"PADDB X1, X0"},
|
|
"i8x16_add_sat_s": {"PADDSB X1, X0"},
|
|
"i8x16_add_sat_u": {"PADDUSB X1, X0"},
|
|
"i8x16_all_true": {"PXOR X3, X3", "PCMPEQB X0, X3", "PMOVMSKB X3, AX", "TESTL AX, AX", "SETEQ AX", "MOVBLZX AX, AX"},
|
|
"i8x16_avgr_u": {"PAVGB X1, X0"},
|
|
"i8x16_bitmask": {"PMOVMSKB X0, AX"},
|
|
"i8x16_eq": {"PCMPEQB X1, X0"},
|
|
"i8x16_ge_s": {"MOVOU X1, X3", "PCMPGTB X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i8x16_ge_u": {"MOVOU X0, X3", "PMAXUB X1, X3", "PCMPEQB X0, X3", "MOVOU X3, X0"},
|
|
"i8x16_gt_s": {"PCMPGTB X1, X0"},
|
|
"i8x16_gt_u": {"MOVOU X0, X3", "PMINUB X1, X3", "PCMPEQB X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i8x16_le_s": {"PCMPGTB X1, X0", "PCMPEQL X4, X4", "PXOR X4, X0"},
|
|
"i8x16_le_u": {"MOVOU X0, X3", "PMINUB X1, X3", "PCMPEQB X0, X3", "MOVOU X3, X0"},
|
|
"i8x16_lt_s": {"MOVOU X1, X3", "PCMPGTB X0, X3", "MOVOU X3, X0"},
|
|
"i8x16_lt_u": {"MOVOU X0, X3", "PMAXUB X1, X3", "PCMPEQB X0, X3", "PCMPEQL X4, X4", "PXOR X4, X3", "MOVOU X3, X0"},
|
|
"i8x16_max_s": {"PMAXSB X1, X0"},
|
|
"i8x16_max_u": {"PMAXUB X1, X0"},
|
|
"i8x16_min_s": {"PMINSB X1, X0"},
|
|
"i8x16_min_u": {"PMINUB X1, X0"},
|
|
"i8x16_narrow_i16x8_s": {"PACKSSWB X1, X0"},
|
|
"i8x16_narrow_i16x8_u": {"PACKUSWB X1, X0"},
|
|
"i8x16_ne": {"PCMPEQB X1, X0", "PCMPEQL X3, X3", "PXOR X3, X0"},
|
|
"i8x16_neg": {"PXOR X3, X3", "PSUBB X0, X3", "MOVOU X3, X0"},
|
|
"i8x16_popcnt": {"MOVOU ·simdConstPopLUT(SB), X3", "MOVOU ·simdConstNib(SB), X4", "MOVOU X0, X5", "PAND X4, X0", "PSRLW $4, X5", "PAND X4, X5", "MOVOU X3, X6", "PSHUFB X0, X6", "PSHUFB X5, X3", "PADDB X6, X3", "MOVOU X3, X0"},
|
|
"i8x16_shl": {"ANDL $7, AX", "MOVQ AX, X3", "MOVL AX, CX", "MOVL $0xff, AX", "SHLL CX, AX", "ANDL $0xff, AX", "IMULL $0x01010101, AX", "MOVQ AX, X4", "PSHUFD $0, X4, X4", "PSLLW X3, X0", "PAND X4, X0"},
|
|
"i8x16_shr_s": {"ANDL $7, AX", "ADDL $8, AX", "MOVQ AX, X3", "MOVOU X0, X5", "PUNPCKLBW X0, X0", "PSRAW X3, X0", "PUNPCKHBW X5, X5", "PSRAW X3, X5", "PACKSSWB X5, X0"},
|
|
"i8x16_shr_u": {"ANDL $7, AX", "MOVQ AX, X3", "MOVL AX, CX", "MOVL $0xff, AX", "SHRL CX, AX", "IMULL $0x01010101, AX", "MOVQ AX, X4", "PSHUFD $0, X4, X4", "PSRLW X3, X0", "PAND X4, X0"},
|
|
"i8x16_shuffle": {"MOVOU ·simdConst70(SB), X3", "MOVOU X2, X4", "PADDUSB X3, X4", "PSHUFB X4, X0", "MOVOU ·simdConst16(SB), X5", "PSUBB X5, X2", "PADDUSB X3, X2", "PSHUFB X2, X1", "POR X1, X0"},
|
|
"i8x16_splat": {"MOVQ AX, X0", "PXOR X3, X3", "PSHUFB X3, X0"},
|
|
"i8x16_sub": {"PSUBB X1, X0"},
|
|
"i8x16_sub_sat_s": {"PSUBSB X1, X0"},
|
|
"i8x16_sub_sat_u": {"PSUBUSB X1, X0"},
|
|
"i8x16_swizzle": {"MOVOU ·simdConst70(SB), X3", "PADDUSB X3, X1", "PSHUFB X1, X0"},
|
|
"v128_and": {"PAND X1, X0"},
|
|
"v128_andnot": {"MOVOU X1, X3", "PANDN X0, X3", "MOVOU X3, X0"},
|
|
"v128_any_true": {"PXOR X3, X3", "PCMPEQB X0, X3", "PMOVMSKB X3, AX", "CMPL AX, $0xffff", "SETNE AX", "MOVBLZX AX, AX"},
|
|
"v128_bitselect": {"PAND X2, X0", "PANDN X1, X2", "POR X2, X0"},
|
|
"v128_not": {"PCMPEQL X3, X3", "PXOR X3, X0"},
|
|
"v128_or": {"POR X1, X0"},
|
|
"v128_xor": {"PXOR X1, X0"},
|
|
}
|
|
|
|
// simdSpliceConsts: the 16-byte tables the bodies reference,
|
|
// interned into the ConstPool at splice time.
|
|
var simdSpliceConsts = map[string][]byte{
|
|
"simdConst16": {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
|
|
"simdConst2p31d": {0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xdf, 0x41, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xdf, 0x41},
|
|
"simdConst2p31f": {0x00, 0x00, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x4f},
|
|
"simdConst65536f": {0x00, 0x00, 0x80, 0x47, 0x00, 0x00, 0x80, 0x47, 0x00, 0x00, 0x80, 0x47, 0x00, 0x00, 0x80, 0x47},
|
|
"simdConst70": {0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70},
|
|
"simdConstAbs32": {0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f},
|
|
"simdConstAbs64": {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f},
|
|
"simdConstBitpos16": {0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00},
|
|
"simdConstBitpos32": {0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00},
|
|
"simdConstBitpos8": {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80},
|
|
"simdConstI16Min": {0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80},
|
|
"simdConstMagicHi": {0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43},
|
|
"simdConstMagicd": {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43},
|
|
"simdConstNib": {0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f},
|
|
"simdConstOnes16": {0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00},
|
|
"simdConstOnes8": {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
|
|
"simdConstPopLUT": {0x00, 0x01, 0x01, 0x02, 0x01, 0x02, 0x02, 0x03, 0x01, 0x02, 0x02, 0x03, 0x02, 0x03, 0x03, 0x04},
|
|
"simdConstSign32": {0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80},
|
|
"simdConstSign64": {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80},
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"simdConstUMaxd": {0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xef, 0x41, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xef, 0x41},
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}
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// a64SimdMemSpliceTab: memory op → guest access size and the
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// body lines run with the checked guest address in R27 (x27).
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var a64SimdMemSpliceTab = map[string]struct {
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Size int
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Lines []string
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}{
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"v128_load": {Size: 16, Lines: []string{"WORD $0x3dc00360 // ldr q0, [x27]"}},
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"v128_load16_splat": {Size: 2, Lines: []string{"WORD $0x4d40c760 // ld1r {v0.8h}, [x27]"}},
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"v128_load16x4_s": {Size: 8, Lines: []string{"WORD $0xfd400360 // ldr d0, [x27]", "WORD $0x0f10a400 // sxtl v0.4s, v0.4h"}},
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"v128_load16x4_u": {Size: 8, Lines: []string{"WORD $0xfd400360 // ldr d0, [x27]", "WORD $0x2f10a400 // uxtl v0.4s, v0.4h"}},
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"v128_load32_splat": {Size: 4, Lines: []string{"WORD $0x4d40cb60 // ld1r {v0.4s}, [x27]"}},
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"v128_load32_zero": {Size: 4, Lines: []string{"WORD $0xbd400360 // ldr s0, [x27]"}},
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"v128_load32x2_s": {Size: 8, Lines: []string{"WORD $0xfd400360 // ldr d0, [x27]", "WORD $0x0f20a400 // sxtl v0.2d, v0.2s"}},
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"v128_load32x2_u": {Size: 8, Lines: []string{"WORD $0xfd400360 // ldr d0, [x27]", "WORD $0x2f20a400 // uxtl v0.2d, v0.2s"}},
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"v128_load64_splat": {Size: 8, Lines: []string{"WORD $0x4d40cf60 // ld1r {v0.2d}, [x27]"}},
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"v128_load64_zero": {Size: 8, Lines: []string{"WORD $0xfd400360 // ldr d0, [x27]"}},
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"v128_load8_splat": {Size: 1, Lines: []string{"WORD $0x4d40c360 // ld1r {v0.16b}, [x27]"}},
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"v128_load8x8_s": {Size: 8, Lines: []string{"WORD $0xfd400360 // ldr d0, [x27]", "WORD $0x0f08a400 // sxtl v0.8h, v0.8b"}},
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"v128_load8x8_u": {Size: 8, Lines: []string{"WORD $0xfd400360 // ldr d0, [x27]", "WORD $0x2f08a400 // uxtl v0.8h, v0.8b"}},
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"v128_store": {Size: 16, Lines: []string{"WORD $0x3d800360 // str q0, [x27]"}},
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}
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