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zeekay
ced35b03ed
Quasar Horizon (consensus composition over Pulsar / ML-DSA / BLS lanes
under Prism + LSS lifecycle), Warp 2.0 (Pulse-backed cross-chain envelope
with forward-only v1->v2 migration and lattigo ReadUint64Slice DoS fix),
benchmark report (microbench, reshare, activation, Warp 2.0 verify, Prism
composition, GPU headroom, cross-WAN latency), and NIST IR 8214C-style
submission package (spec, parameter sets, domain separation, serialization,
reference-impl pointers, evaluation report, security analysis, side-channel
considerations).
All four deliverables compile cleanly via pdflatex+bibtex and reference
the canonical proof bucket files at proofs/{definitions,pulsar,lss,quasar}.
No duplication of proof bodies; cite by file path.
30 lines
1.6 KiB
TeX
30 lines
1.6 KiB
TeX
\section*{Addendum: Optimized GPU Kernel}
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After switch-based opcode dispatch and compact stack optimization,
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the GPU Metal EVM achieves 2,303 million opcodes/second (2.3 Gops/s)
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on Apple M1 Max. This represents a 12.1$\times$ speedup over the
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C++ CPU interpreter (191 Mops/s) and approximately 115$\times$ over
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the Go EVM interpreter. Gas accounting verified identical between
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GPU and CPU execution paths across all test cases.
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At Lux's 1\,B gas block limit ($\sim$47{,}619 txs/block at 21{,}000 gas/tx),
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the GPU kernel processes a full block in $\sim$10\,ms execution time.
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Combined with GPU-accelerated BLS consensus (10\,ms per round), this
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yields \textbf{\num{4761904} TPS with finality}.
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\paragraph{BLS pairing host-vs-Metal accounting.}
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The ``GPU-accelerated BLS consensus'' on Apple M1 Max is the
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cevm v0.45 same-message batched aggregate verifier (lifted to
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$16.51\times$ at $n{=}1024$ in cevm v0.47.1, commit \texttt{6bf0e232},
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via a 4096-slot pubkey-decompression cache). The pairing math
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itself remains the canonical \texttt{luxcpp/crypto/bls} c-abi body,
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which is host-CPU on Apple Silicon: Stage 5b measurement
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(luxcpp/crypto \texttt{9ff799fd}, 2026-04-27) showed pure-Metal
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single-pairing at ${\sim}475\,\text{ms}$ vs ${\sim}510\,\mu\text{s}$
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host blst (${\sim}930\times$ slower) due to ${\sim}280$ dispatches
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per pairing on the serial Fp12 chain. The architecture is byte-equal
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blst across 2 746 vectors; the SoTA single-pairing path is Linux+CUDA
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or batched-N parallel kernel saturation. Production cevm + bridgevm
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binaries link zero blst symbols (cevm v0.46.0, CI-asserted).
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