papers/lp-205-pipelined-quasar/sections/05-throughput.tex

\section{Wall-Clock Throughput Model}

The throughput model at depth $D$:

\begin{equation}
\textrm{throughput} = \frac{D}{\sum(\textrm{stage\_times})}
\quad\text{or, at steady-state with } D = \#\textrm{stages} = 3,\quad
\textrm{throughput} = \frac{1}{\max(\textrm{stage\_times})}.
\end{equation}

\subsection{Cross-mode measurements}

Reference numbers from the Quasar matrix bench
(\texttt{/tmp/quasar-matrix-bench/matrix\_bench\_test.go}, run
2026-06-04) on Spark (NVIDIA GB10 Grace Blackwell sm\_120,
20-core ARM, CUDA 13.0.88) at $N{=}64$ validators, crossed with
the LP-202 pipeline-depth saturation. Sign-stage cert wall-clocks
are per-cert (\texttt{ns/total} column of the bench output);
Select+Build is the LP-205 prep envelope, projected from LP-010
Block-STM + ZAP encoder bench rows. The Sign column is
\textbf{measured} on CPU-only (Pulsar + Corona) -- GPU offload of
Pulsar/Corona/Magnetar exists in the kernels (LP-203) but the
verify wrappers were NotSupported on the run date, so the matrix
bench did not exercise GPU. GPU-accelerated cert wall-clocks
remain projected.

\begin{table}[h]
\centering
\small
\begin{tabular}{@{}lrrrl@{}}
\toprule
\textbf{Mode} & \textbf{Sign} & \textbf{Sel+Build} & \textbf{tput @ $D{=}3$} & \textbf{Source} \\
\midrule
PQ-off & \SI{6.3}{\milli\second} & \SI{3}{\milli\second} & $\sim 158$ b/s & measured Spark $N{=}64$ \\
PQ-fast (CPU) & \SI{585}{\milli\second} & \SI{3}{\milli\second} & $\sim 1.7$ b/s & measured Spark $N{=}64$ \\
PQ-strict (CPU) & \SI{595}{\milli\second} & \SI{3}{\milli\second} & $\sim 1.7$ b/s & measured Spark $N{=}64$ \\
PQ-heavy (CPU) & \SI{1326}{\milli\second} & \SI{3}{\milli\second} & $\sim 0.75$ b/s & measured Spark $N{=}64$ \\
\addlinespace
PQ-fast (GPU) & $\sim$\SI{5}{\milli\second} & \SI{3}{\milli\second} & $\sim 200$ b/s & projected (LP-203) \\
PQ-strict (GPU) & $\sim$\SI{15}{\milli\second} & \SI{3}{\milli\second} & $\sim 65$ b/s & projected (LP-203) \\
PQ-heavy (GPU) & $\sim$\SI{80}{\milli\second} & \SI{3}{\milli\second} & $\sim 12$ b/s & projected (LP-203) \\
\bottomrule
\end{tabular}
\caption{Per-mode steady-state throughput at depth $D{=}3$.
Top block: \textbf{measured} cert wall-clocks from the 2026-06-04
quasar-matrix-bench run on Spark (\texttt{/tmp/quasar-results-spark.txt}),
$N{=}64$. Bottom block: \textbf{projected} GPU-accelerated cert
wall-clocks per LP-203 \S{}``NVIDIA GB10 Grace Blackwell sm\_120''
once the verify-side wrappers (Magnetar, ML-DSA, Ed25519, sr25519)
ship -- the underlying kernels are operational and the BLS pairing
rate (49\,197 pairings/sec, 19\,$\mu$s/pair) is measured.}
\label{tab:throughput}
\end{table}

\subsection{Sweet spot}

Pipelining wins are largest when stage times are balanced. On the
measured CPU-only Spark $N{=}64$ rows the cert dominates by
$\sim 200\times$ over Select+Build across PQ-fast and PQ-strict,
so pipelining gain is marginal (cert-limited). The sweet spot is
the \emph{projected} GPU-accelerated PQ-fast row: cert wall-clock
$\sim$\SI{5}{\milli\second} versus prep $\sim$\SI{3}{\milli\second}
gives depth-3 throughput $1/$\SI{5}{\milli\second} $=$
\SI{200}{\,blocks\per\second} vs round-blocking
$1/$\SI{8}{\milli\second} $=$ \SI{125}{\,blocks\per\second} -- a
$60\%$ win. \textbf{This row is projected, not measured} -- it
assumes Pulsar/Corona/Magnetar verify wrappers ship on the GB10
kernel substrate (LP-203). The pairing-rate measurements
(49\,197 pairings/sec at 19\,$\mu$s/pair) are consistent with
this projection.

At PQ-heavy mode the matrix bench measured \SI{1326}{\milli\second}
cert wall-clock on CPU; depth-3 pipelining yields
$\sim$\SI{0.75}{\,blocks\per\second} versus round-blocking
$\sim$\SI{0.75}{\,blocks\per\second} -- essentially the same,
because the cert dominates. Pipelining is not the highest-leverage
optimization for PQ-heavy chains on CPU; GPU-accelerated Magnetar
(LP-181 follow-up, LP-203 kernels operational, wrappers pending)
is. The Magnetar SLH-DSA-192s sign at \SI{795}{\milli\second} is
the dominant component of the measured PQ-heavy wall-clock; the
22$\times$ faster 192f variant (\SI{36}{\milli\second}/sign) closes
most of that gap if substituted.

\subsection{Beyond depth 3}

Depth~$4{+}$ does not gain throughput because there are only three
stages. Additional depth would require either pipelining across
heights at the cert level (out of scope; would be a HotStuff-2B
4-phase pipeline) or restructuring the per-block stage list.
Neither is in scope for this LP.

\subsection{Honest reading of the projections}

The four CPU-only cert wall-clocks in the top half of
Table~\ref{tab:throughput} are \textbf{measured} on Spark at
$N{=}64$ on 2026-06-04 (\texttt{/tmp/quasar-results-spark.txt}).
The matrix bench ran the full 7-cert-profile $\times$ 4-validator-count
sweep with the actual ceremony machinery (Pulsar threshold,
Corona aggregation, Magnetar SLH-DSA). GPU was not exercised
(mean SM\%${=}11.9\%$ across 4\,595 \texttt{nvidia-smi dmon}
samples) because the Magnetar/ML-DSA/Ed25519/sr25519 verify
wrappers were not yet wired into the bench at run time;
underlying kernels are operational per LP-203.

The Select+Build estimate is projected: the Block-STM ordering pass
(LP-010 measured at $\sim$\SI{1.2}{\milli\second} for a $1000$-tx
block on M4 Max) plus the ZAP encoder (measured at
$\sim$\SI{150}{\micro\second} per block of $1000$ txs) plus the
mempool sample pass ($\sim$\SI{1}{\milli\second} heap traversal).
Summed: $\sim$\SI{3}{\milli\second}, projected.

The projected GPU-accelerated rows in the bottom of
Table~\ref{tab:throughput} carry over from prior LP-203 single-leg
bench rows (Blackwell sm\_120 pairing rates: 49\,197 pairings/sec
sustained, 19\,$\mu$s/pair, 4\,W power draw, 12\,300 pairings/watt)
extrapolated to the steady-state $\max(\textrm{stages})$ formula.
The pairing-rate measurement is a verified upper bound on the
Pulsar verify throughput; the Magnetar SLH-DSA-192s verify is the
binding constraint at PQ-heavy.

\paragraph{Depth-3 pipelining is consistent with the matrix bench
data.} At PQ-off ($N{=}64$, Spark), the matrix bench observed
6.3~ms per-cert wall-clock and 33.6~ms total ceremony cost
(\texttt{ns/op} field). The 5.3$\times$ ratio between ceremony cost
and per-cert wall-clock matches the LP-202 stage-list orthogonality:
the ceremony cost is the sum of stage times, the per-cert wall-clock
is one stage time, and depth-3 pipelining drives the per-block
wall-clock toward the per-cert (sign-stage) value. The pipelining
claim is validated by the ratio, even though the matrix bench did
not run pipelined Quasar end-to-end.