papers/evmgpu-benchmark/evmgpu-benchmark.tex

\documentclass[11pt]{article}
\usepackage{../shared/luxcover}
\usepackage{amsmath,amssymb}
\usepackage{graphicx}
\usepackage{booktabs}
\usepackage{hyperref}
\usepackage{listings}
\usepackage{xcolor}
\usepackage{tikz}
\usepackage{pgfplots}
\pgfplotsset{compat=1.18}
\usepackage{siunitx}
\usepackage{multirow}
\usepackage{subcaption}
\usetikzlibrary{arrows.meta,positioning,calc}

\sisetup{group-separator={,}}

\definecolor{luxblue}{RGB}{30,64,175}
\definecolor{luxgold}{RGB}{234,179,8}
\definecolor{gpugreen}{RGB}{22,163,74}
\definecolor{cpured}{RGB}{220,38,38}
\definecolor{cppblue}{RGB}{37,99,235}
\definecolor{gogreen}{RGB}{0,125,156}

\title{The Unified GPU-Native Multichain Engine:\\
Measured Benchmarks of EVM Execution, DEX Matching, and FHE\\
from Apple M1 Max Metal to NVIDIA GB10 and AMD RDNA}
\author{
Lux Research\thanks{Corresponding author: [email protected]}\\
\textit{Lux Industries, Inc.}\\
\texttt{[email protected]}
}
\date{2026}

\begin{document}

\luxcoverpage

\begin{abstract}
We present measured benchmarks of GPU-accelerated Ethereum Virtual Machine (EVM) execution
on Apple M1 Max with 32-core Metal GPU and 64\,GB unified memory. The GPU EVM kernel
achieves 85.9\,M opcodes/sec versus 17.7\,M opcodes/sec on CPU---a \textbf{4.85$\times$ peak speedup}.
GPU acceleration becomes advantageous above $\sim$500 opcodes per transaction, reaching
2.08$\times$ at 2{,}000 ops/tx, 2.83$\times$ at 5{,}000 ops/tx, and 3.09$\times$ at 10{,}000 ops/tx.

Independent of GPU work, the C++ evmone interpreter with a full state layer achieves
20.9\,Ggas/s (best: 23.4\,Ggas/s)---\textbf{5.1$\times$ faster} than the Go EVM's 4.2--5.4\,Ggas/s
on EVM-only execution. Profiling confirms that \textbf{87\% of Go block processing} is
secp256k1 ecrecover; parallelizing ecrecover across 10 CPU cores yields 7.1$\times$ speedup.

The system is validated by 1{,}183 tests across C++/Rust/Go, 35 Metal shaders and 11 WGSL
shaders (all compiling clean), 14 host dispatch functions, and 8 GPU state DB tests passing.

\vspace{0.5em}
\noindent\textbf{Production-silicon results (this revision).} We extend the study to the two
accelerators that ship in the Lux high-frequency settlement fabric and, decisively, to the
\emph{deterministic} DEX matching engine. The measured kernel is the consensus-path
central-limit-order-book matcher itself---one thread per order book walking that book in strict
price-time priority (sequential within a book, so every validator re-executes bit-identically),
with millions of books resolved in parallel across the grid, and GPU$=$CPU fill-parity verified
on every run. Coalescing the resting-book layout (array-of-structs $\to$ order-major
structure-of-arrays) and tuning threads-per-block and register residency per backend lifts each
discrete accelerator $5.9$--$6.6\times$ over its own baseline: the matcher sustains
\textbf{12.76\,billion orders/sec} on an AMD Radeon 8060S (RDNA, \textbf{12.5$\times$} its 32-core
CPU) and \textbf{9.13\,billion orders/sec} on an NVIDIA GB10 Grace-Blackwell
(\textbf{17.5$\times$} its 20-core Grace CPU), a two-node aggregate of
\textbf{21.9\,billion orders/sec}---all on the deterministic path, not an aggregated-liquidity
approximation. Two findings generalize: coalescing is a discrete/APU-memory optimization
(neutral-to-negative on Apple unified memory, where the M4~Max's tuned optimum is instead the
array-of-structs layout at \SI{5.60}{\giga\text{orders}/\second}), and the two discrete vendors
want opposite register strategies (the occupancy-bound GB10 prefers low register pressure and
32-thread blocks; the bandwidth-rich 8060S prefers register-resident data at 64-thread blocks).
This raw matching rate is a compute ceiling that the network and consensus layers bind well
beneath: the inter-node link---a tuned \SI{2.5}{\giga bit/\second} Ethernet---sustains
\SI{2.35}{\giga bit/\second} at 94\% of line rate with zero retransmissions, and post-quantum
ML-DSA-65 (FIPS~204) signing and verification are measured at \SI{450}{\micro\second} and
\SI{134}{\micro\second} respectively. Under \emph{batch attestation} (one post-quantum signature
per block over a BLS-aggregated fast path), a single colocated two-GPU venue is \emph{projected}
to admit \textbf{$\sim$1.79\,billion orders/sec} over \SI{800}{\giga bit/\second} InfiniBand
(network-bound, a $12\times$ compute margin over the wire); at that ceiling the fabric clears peak
world \emph{traded} order flow with substantial headroom while remaining fully post-quantum.
Signing every order individually on the wire, by contrast, is signature-size-bound to
\SI{88}{\kilo\text{orders}/\second}.
\end{abstract}

\tableofcontents
\newpage

\input{sections/01-introduction}
\input{sections/02-hardware-and-environment}
\input{sections/03-gpu-evm-kernel-benchmarks}
\input{sections/04-c-evm-vs-go-evm}
\input{sections/05-profiling-the-signature-bottleneck}
\input{sections/06-gpu-shader-inventory}
\input{sections/07-test-coverage}
\input{sections/08-block-stm-parallel-execution}
\input{sections/09-gpu-acceleration-cryptographic-operation}
\input{sections/10-discussion}
\input{sections/11-gpu-clob-matcher}
\input{sections/12-addendum-optimized-gpu-kernel}
\input{sections/13-named-competitor-comparison}
\input{sections/14-production-silicon-dex-and-e2e}
\input{sections/15-operation-accounting}
\input{sections/16-replication}
\input{sections/99-conclusion}

\end{document}