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zeekayandHanzo Dev
61863ad91c
Fold the measured, tuned GPU results across all three GPU makers into the paper. The deterministic consensus-path CLOB matcher (one thread per book, sequential price-time priority, GPU=CPU fill-parity verified) becomes the headline, replacing the earlier batch-matcher framing: AMD Radeon 8060S (HIP, SoA preload TPB=64): 12.76B ord/s (1.94B baseline, 6.6x) NVIDIA GB10 (CUDA, SoA lowreg TPB=32): 9.13B ord/s (1.54B baseline, 5.9x) Apple M4 Max (Metal, AoS TPB=256): 5.60B ord/s Apple M1 Max (Metal, SoA TPB=256): 2.80B ord/s Two-node fabric aggregate: 21.9B ord/s Findings: memory coalescing (AoS->order-major SoA) is a discrete/APU-memory win, neutral-to-negative on Apple unified memory; NVIDIA is occupancy-bound (prefers lowreg + small blocks) while AMD is bandwidth-rich (prefers register preload) -- opposite optima. Determinism and throughput are not in tension: parallelism goes across books, sequential within. Updated abstract, sec 14 (production silicon), sec 15 (operation accounting incl blend table -> 21.9B pure-match aggregate), sec 12 (execution-only TPS honesty), conclusion. Harnesses live in luxfi/gpu dex/bench. Compiles clean, 25 pages. Co-authored-by: Hanzo Dev <[email protected]>
35 lines
1.9 KiB
TeX
35 lines
1.9 KiB
TeX
\section*{Addendum: Optimized GPU Kernel}
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After switch-based opcode dispatch and compact stack optimization,
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the GPU Metal EVM achieves 2,303 million opcodes/second (2.3 Gops/s)
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on Apple M1 Max. This represents a 12.1$\times$ speedup over the
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C++ CPU interpreter (191 Mops/s) and approximately 115$\times$ over
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the Go EVM interpreter. Gas accounting verified identical between
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GPU and CPU execution paths across all test cases.
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At Lux's 1\,B gas block limit ($\sim$47{,}619 txs/block at 21{,}000 gas/tx),
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the optimized GPU kernel processes a full block in $\sim$10\,ms of
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\emph{opcode-execution} time---an execution-only upper bound of $\sim$4.8\,M TPS.
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This is \emph{not} an end-to-end finality figure: it excludes signature
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recovery (ecrecover is 87\% of Go block time), the settlement
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conflict-detector (\SI{2.2}{\mega\text{fills}/\second},
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Section~\ref{sec:clob}), and BLS pairing---which on this Apple Silicon runs on
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the host CPU (see below), not the GPU. End-to-end throughput with post-quantum
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finality is bound by those layers, not by opcode dispatch.
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\paragraph{BLS pairing host-vs-Metal accounting.}
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The ``GPU-accelerated BLS consensus'' on Apple M1 Max is the
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cevm v0.45 same-message batched aggregate verifier (lifted to
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$16.51\times$ at $n{=}1024$ in cevm v0.47.1, commit \texttt{6bf0e232},
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via a 4096-slot pubkey-decompression cache). The pairing math
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itself remains the canonical \texttt{luxcpp/crypto/bls} c-abi body,
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which is host-CPU on Apple Silicon: Stage 5b measurement
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(luxcpp/crypto \texttt{9ff799fd}, 2026-04-27) showed pure-Metal
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single-pairing at ${\sim}475\,\text{ms}$ vs ${\sim}510\,\mu\text{s}$
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host blst (${\sim}930\times$ slower) due to ${\sim}280$ dispatches
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per pairing on the serial Fp12 chain. The architecture is byte-equal
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blst across 2 746 vectors; the SoTA single-pairing path is Linux+CUDA
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or batched-N parallel kernel saturation. Production cevm + bridgevm
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binaries link zero blst symbols (cevm v0.46.0, CI-asserted).
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