Files
zeekayandHanzo Dev 61863ad91c evmgpu-benchmark: tuned deterministic per-book matcher, up to 12.76B ord/s
Fold the measured, tuned GPU results across all three GPU makers into the paper.
The deterministic consensus-path CLOB matcher (one thread per book, sequential
price-time priority, GPU=CPU fill-parity verified) becomes the headline, replacing
the earlier batch-matcher framing:

  AMD Radeon 8060S (HIP, SoA preload TPB=64): 12.76B ord/s (1.94B baseline, 6.6x)
  NVIDIA GB10      (CUDA, SoA lowreg TPB=32):  9.13B ord/s (1.54B baseline, 5.9x)
  Apple M4 Max     (Metal, AoS TPB=256):       5.60B ord/s
  Apple M1 Max     (Metal, SoA TPB=256):       2.80B ord/s
  Two-node fabric aggregate:                  21.9B ord/s

Findings: memory coalescing (AoS->order-major SoA) is a discrete/APU-memory win,
neutral-to-negative on Apple unified memory; NVIDIA is occupancy-bound (prefers
lowreg + small blocks) while AMD is bandwidth-rich (prefers register preload) --
opposite optima. Determinism and throughput are not in tension: parallelism goes
across books, sequential within.

Updated abstract, sec 14 (production silicon), sec 15 (operation accounting incl
blend table -> 21.9B pure-match aggregate), sec 12 (execution-only TPS honesty),
conclusion. Harnesses live in luxfi/gpu dex/bench. Compiles clean, 25 pages.

Co-authored-by: Hanzo Dev <[email protected]>
2026-07-02 00:13:01 -07:00

141 lines
5.6 KiB
TeX

\section{Conclusion}
Measured benchmarks demonstrate four independent acceleration vectors, from Apple M1 Max Metal
to production NVIDIA GB10 and AMD RDNA silicon:
\begin{enumerate}
\item \textbf{GPU EVM kernel}: 85.9\,M opcodes/sec, 4.85$\times$ peak speedup over CPU.
GPU wins above 500 opcodes/tx, reaching 3.09$\times$ at 10{,}000 ops/tx.
\item \textbf{C++ interpreter}: 20.9\,Ggas/s with full state (5.1$\times$ over Go EVM).
416\,Ggas/s interpreter-only.
\item \textbf{Parallel ecrecover}: 7.1$\times$ on 10 cores. This is the highest-leverage
single optimization because ecrecover consumes 87\% of block processing time.
\item \textbf{Production DEX matching}: on shipping accelerators, the \emph{deterministic}
consensus-path matcher (one thread per book, coalesced and tuned per backend, GPU$=$CPU
parity-verified) reaches \textbf{12.76\,billion orders/sec} on an AMD Radeon 8060S
($12.5\times$ its 32-core CPU) and \textbf{9.13\,billion orders/sec} on an NVIDIA GB10
($17.5\times$ its Grace CPU)---$5.9$--$6.6\times$ over each part's un-coalesced baseline---
aggregating to \SI{21.9}{\giga\text{ord}/\second} across a two-node network.
\end{enumerate}
GPU memory scales linearly at 73\,KB/tx, supporting up to 800k transactions per block
on 64\,GB unified memory. The system is validated by 1{,}183 tests across C++, Rust, Go,
Metal, and WGSL.
These optimizations are orthogonal and composable: parallel ecrecover + C++ EVM +
GPU crypto + Block-STM can be combined for multiplicative throughput gains.
\paragraph{The unified engine, end to end.} Composing the measured layers---billion-order GPU
matching, a tuned \SI{2.35}{\giga bit/\second} inter-node link at 94\% of line rate, and
post-quantum ML-DSA-65 at \SI{134}{\micro\second} verification---a single colocated two-GPU
venue over \SI{800}{\giga bit/\second} InfiniBand admits an estimated
\SI{1.79}{\giga\text{orders}/\second}, exceeding the \emph{entire world's traded order flow} by
more than two orders of magnitude while remaining fully post-quantum and, modulo an estimated
$\sim$5--15\% confidential-compute overhead, fully confidential. Because the DEX matcher, the
native GPU EVM (\texttt{block\_stm\_execute\_kernel} and companions), and the 28-kernel FHE layer
(NTT primitive at $23.6\times$ over CPU) share one unified-memory address space and a single
dispatch stream, a confidential order is matched, settled, and homomorphically processed without
ever leaving the accelerator. This is the defining property of the Lux unified GPU-native
multichain engine: the empirical case that a post-quantum, confidential, GPU-native settlement
fabric can clear all of the world's markets from a single colocated site.
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% --- Named-competitor scaffold (Apr 2026) ---
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