papers/lp-209-mysticeti-ordering/sections/03-throughput-latency.tex

\section{Throughput and Latency}

Reference numbers from a 40-validator LAN at $K{=}4$ parents per
header, $T{=}500$ txs per header, round cadence
\SI{50}{\milli\second}.

\subsection{Throughput}

\begin{table}[h]
\centering
\small
\begin{tabular}{@{}p{6cm}rl@{}}
\toprule
\textbf{Quantity} & \textbf{Value} & \textbf{Source} \\
\midrule
Headers per wave (typical) & $\geq 40 \times 2 = 80$ & every validator publishes 2 headers per wave \\
Txs per wave & $80 \times 500 = 40{,}000$ & header count $\times$ tx count \\
Wave cadence & \SI{50}{\milli\second} $\times 2 = $ \SI{100}{\milli\second} & 2 rounds per wave \\
Waves/sec at cadence floor & 10 & $1/$\SI{100}{\milli\second} \\
Txs/sec at cadence floor (1 wave) & \SI{400}{\kilo tx/s} & $40$k $\times$ 10 \\
Txs/sec at 3-deep pipelining (LP-205) & \SI{1.2}{\mega tx/s} & 3$\times$ pipeline depth \\
\bottomrule
\end{tabular}
\caption{Throughput at the LAN protocol floor. \textbf{Projected,
not measured} -- assumes the projected GPU-accelerated cert path
of LP-203 holds the wave cadence below \SI{100}{\milli\second}.
The 2026-06-04 quasar-matrix-bench measured CPU-only cert
wall-clocks (Spark $N{=}64$: PQ-fast \SI{585}{\milli\second},
PQ-strict \SI{595}{\milli\second}, PQ-heavy
\SI{1326}{\milli\second}, \texttt{/tmp/quasar-results-spark.txt})
exceed the \SI{100}{\milli\second} cadence in every PQ row, so this
floor is achievable only with GPU offload (LP-203 wrappers, pending).}
\label{tab:throughput}
\end{table}

The \SI{1.2}{\mega tx/s} figure is the projected protocol-floor
throughput at LAN scale under GPU-accelerated cert. On the measured
CPU-only cert path, the wave cadence is cert-bottlenecked at
$\sim$\SI{585}{\milli\second} (PQ-fast Spark $N{=}64$) or higher,
so aggregate at 3-deep pipelining drops to $\sim$\SI{205}{\kilo tx/s}.
At WAN scale ($\sim$\SI{150}{\milli\second} RTT,
$\sim$\SI{50}{\milli\second} round cadence held by overlap
gossiping) the wave cadence rises to $\sim$\SI{300}{\milli\second};
aggregate falls to $\sim$\SI{400}{\kilo tx/s} (projected GPU path)
or stays cert-bottlenecked at $\sim$\SI{205}{\kilo tx/s} (measured
CPU path) -- still saturates the LP-210 per-validator execution budget.

\subsection{Latency}

Path to finality for a tx admitted at time $t = 0$. Two reference
columns: the projected GPU-accelerated cert path and the
2026-06-04 matrix-bench measured CPU-only cert path.

\begin{table}[h]
\centering
\small
\begin{tabular}{@{}p{5.4cm}rrp{3.6cm}@{}}
\toprule
\textbf{Event} & \textbf{GPU proj.} & \textbf{CPU meas.} & \textbf{Path} \\
\midrule
Tx admitted to mempool & \SI{0}{\milli\second} & \SI{0}{\milli\second} & LP-208 tx receive \\
Header containing tx published & $\leq$~\SI{25}{\milli\second} & $\leq$~\SI{25}{\milli\second} & LP-208 round cadence, half-round budget \\
Header referenced by $\geq 2f{+}1$ in next round & $\leq$~\SI{75}{\milli\second} & $\leq$~\SI{75}{\milli\second} & + 1 round (\SI{50}{\milli\second} cadence) \\
Wave anchor decided (round $2k{+}1$) & $\leq$~\SI{100}{\milli\second} & $\leq$~\SI{100}{\milli\second} & + 1 round to count references \\
Wave ordered + LP-210 exec begins & $\leq$~\SI{105}{\milli\second} & $\leq$~\SI{105}{\milli\second} & causal sort $O(|W|)$ \\
LP-210 exec complete (40k tx batch, 16-core) & $\leq$~\SI{115}{\milli\second} & $\leq$~\SI{115}{\milli\second} & $\sim$\SI{10}{\milli\second} for 40k txs \\
LP-217 cert at PQ-strict & $\leq$~\SI{120}{\milli\second} & $\leq$~\SI{710}{\milli\second} & GPU: $+\,\sim$\SI{5}{\milli\second}; CPU: $+\,\sim$\SI{595}{\milli\second} (matrix bench Spark $N{=}64$) \\
ZapDB commit & $\leq$~\SI{121}{\milli\second} & $\leq$~\SI{711}{\milli\second} & LP-202 atomic commit, $O(1)$ at MVCC layer \\
\bottomrule
\end{tabular}
\caption{End-to-end LAN latency to PQ-strict finality. GPU column
is projected (LP-203 pairing-rate measurement extrapolated); CPU
column is grounded in the 2026-06-04 quasar-matrix-bench cert
wall-clock (\texttt{/tmp/quasar-results-spark.txt}, $N{=}64$,
PQ-strict row).}
\label{tab:latency}
\end{table}

\paragraph{Summary.} End-to-end LAN finality at PQ-strict:
$\sim$\SI{120}{\milli\second} (\textbf{projected} GPU-accelerated
path), $\sim$\SI{711}{\milli\second} (\textbf{measured} CPU-only
path, 2026-06-04 matrix bench Spark $N{=}64$). At PQ-heavy:
projected GPU adds $\sim$\SI{80}{\milli\second} for Magnetar
$\to$ $\sim$\SI{200}{\milli\second}; measured CPU adds
\SI{1326}{\milli\second} (matrix bench Spark $N{=}64$ PQ-heavy row)
$\to$ $\sim$\SI{1441}{\milli\second}. Under $<50\%$ byzantine
(3-RTT path), add one extra round ($\sim$\SI{50}{\milli\second}).

\subsection{Honest reading of the projections}

\textbf{Measured cert-leg numbers.} The earlier 2026-04
multi-validator harness (\texttt{/tmp/multi-validator/result-100v-hybrid.json})
recorded $N{=}100$ validators with Pulsar p50 = \SI{297.5}{\milli\second},
BLS p50 = \SI{161.6}{\milli\second}, Corona p50 = \SI{2593}{\milli\second}
under the Hybrid profile on CPU. The 2026-06-04 quasar-matrix-bench
on Spark at $N{=}64$ refines this with the full 7-cert-profile
sweep: PQ-off \SI{6.3}{\milli\second}, PQ-fast
\SI{585}{\milli\second}, PQ-strict \SI{595}{\milli\second}, PQ-heavy
\SI{1326}{\milli\second} per-cert wall-clock. Both rounds are CPU-only;
GPU was not exercised (mean SM\%${=}11.9\%$).

\textbf{Projected GPU-accelerated numbers.} The LP-203 GB10
sm\_120 BLS12-381 pairing measurement (49\,197 pairings/sec,
19\,$\mu$s/pair, 4\,W) and the keccak256 batch
(\SI{11.38}{\mega ops/s}) are measured and operational. With the
Pulsar / Corona verify wrappers wired in (currently NotSupported),
the projected PQ-fast GPU-accelerated cert wall-clock is
$\sim$\SI{5}{\milli\second}; PQ-strict $\sim$\SI{15}{\milli\second};
PQ-heavy $\sim$\SI{80}{\milli\second}. These remain projections
until the wrappers ship.

\textbf{Throughput-floor sensitivity.} The
Table~\ref{tab:throughput} \SI{1.2}{\mega tx/s} number assumes the
projected GPU path. On the measured CPU-only path, throughput is
cert-bottlenecked: PQ-fast yields
$1/$\SI{585}{\milli\second}${} \times 40$k txs/wave${} \times 3$
(pipeline) $\approx$ \SI{205}{\kilo tx/s}, not
\SI{1.2}{\mega tx/s}. The pipelining and DAG-throughput claims
hold structurally; GPU offload (LP-203 wrappers) closes the
6$\times$ gap.