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First measured scaling laws for post-quantum threshold consensus on heterogeneous hardware. Real numbers from M1 Max with wgpu-native 29.0.0 (real WebGPU, not polyfill). Main findings: * CPU per-NTT cost flat at ~1.4 us across n=1..65536. * Metal: 1.5 ms per dispatch, crosses CPU at n~3260, peaks 1.48x at n=65536. * WGSL: 2.7 ms per dispatch, asymptotic per-op (1.58 us) HIGHER than CPU (1.38 us) — never crosses on M1 Max. Constraint: uint32-emulated u64 vs Metal's native u64. * Pulsar production hot path n=2688 sits below both crossovers. Per-validator GPU acceleration unprofitable; aggregator-side multi-validator batching wins. Three empirical scaling laws derived: * L1 batch-size law: T_GPU/poly(n) = D/n + tau, crossover n* = D/(tau_CPU - tau_GPU). * L2 validator-parallelism law: aggregator amortizes dispatch over k validators. * L3 epoch-amortization law: workloads that batch at epoch boundary cross n* far earlier. Sections (660 LoC of LaTeX): 01-introduction — claim summary + sharpest finding 02-methodology — bench harness, hardware, threats to validity 03-measurements — TSV-grade tables of NTT sweep + workload-level (ZAP, FHE, reshare) 04-scaling-laws — three theorems with fitted constants 05-implications — concrete posture for backend.Policy defaults 06-honesty — what was measured vs not (NVIDIA, Block-STM, DEX, e2e) 99-conclusion — production posture + queued workstreams Data/ directory carries the raw TSV (ntt-sweep-m1max-2026-05-04.tsv) emitted by the new corona_lattice_ring_sweep_bench. Honest scope: NVIDIA H100, Block-STM parallel EVM throughput, DEX matching engine, and end-to-end consensus+EVM+DEX+FHE pipeline are all queued for v0.3.0; not in this paper. Section 06 documents the boundary.