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43 lines
1.0 KiB
TeX
43 lines
1.0 KiB
TeX
\section{Boolean Gate Performance}
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Each boolean gate includes a full bootstrapping operation (blind rotation + sample extraction + optional key switching).
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\begin{table}[h]
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\centering
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\begin{tabular}{@{}lrr@{}}
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\toprule
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\textbf{Gate} & \textbf{EPYC} & \textbf{M2} \\
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\midrule
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AND & 8.2 ms & 12.1 ms \\
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OR & 8.1 ms & 12.0 ms \\
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XOR & 8.3 ms & 12.2 ms \\
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NOT & 0.01 ms & 0.01 ms \\
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NAND & 8.2 ms & 12.1 ms \\
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MUX (ternary) & 16.5 ms & 24.3 ms \\
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MAJORITY & 24.8 ms & 36.4 ms \\
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\bottomrule
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\end{tabular}
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\caption{Boolean gate latency (PN10QP27). NOT is a trivial negation without bootstrapping. MUX requires 2 AND + 1 OR + bootstrapping.}
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\label{tab:gates}
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\end{table}
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\subsection{Gate Throughput (Multi-threaded)}
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\begin{table}[h]
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\centering
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\begin{tabular}{@{}lrr@{}}
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\toprule
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\textbf{Threads} & \textbf{EPYC (AND/s)} & \textbf{M2 (AND/s)} \\
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\midrule
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1 & 122 & 83 \\
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4 & 480 & 320 \\
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16 & 1,890 & --- \\
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64 & 7,200 & --- \\
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\bottomrule
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\end{tabular}
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\caption{AND gate throughput with parallel bootstrapping.}
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\label{tab:gate-throughput}
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\end{table}
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