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papers/lux-fhe-benchmarks/sections/05-boolean-gate-performance.tex
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\section{Boolean Gate Performance}
Each boolean gate includes a full bootstrapping operation (blind rotation + sample extraction + optional key switching).
\begin{table}[h]
\centering
\begin{tabular}{@{}lrr@{}}
\toprule
\textbf{Gate} & \textbf{EPYC} & \textbf{M2} \\
\midrule
AND & 8.2 ms & 12.1 ms \\
OR & 8.1 ms & 12.0 ms \\
XOR & 8.3 ms & 12.2 ms \\
NOT & 0.01 ms & 0.01 ms \\
NAND & 8.2 ms & 12.1 ms \\
MUX (ternary) & 16.5 ms & 24.3 ms \\
MAJORITY & 24.8 ms & 36.4 ms \\
\bottomrule
\end{tabular}
\caption{Boolean gate latency (PN10QP27). NOT is a trivial negation without bootstrapping. MUX requires 2 AND + 1 OR + bootstrapping.}
\label{tab:gates}
\end{table}
\subsection{Gate Throughput (Multi-threaded)}
\begin{table}[h]
\centering
\begin{tabular}{@{}lrr@{}}
\toprule
\textbf{Threads} & \textbf{EPYC (AND/s)} & \textbf{M2 (AND/s)} \\
\midrule
1 & 122 & 83 \\
4 & 480 & 320 \\
16 & 1,890 & --- \\
64 & 7,200 & --- \\
\bottomrule
\end{tabular}
\caption{AND gate throughput with parallel bootstrapping.}
\label{tab:gate-throughput}
\end{table}