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zeekayandHanzo Dev
e2cb62c540
I resolved these files toward a June commit that called the billion-order figures fabricated, and that commit was itself the mistaken one. The July campaign it predates does not assert its numbers, it checks them: a GPU-versus-CPU parity run matching exactly, 38,000,000 fills on both sides at 1,000,000 books, depth 32, 32 takers each, on hardware this estate owns. It also names the error in the earlier framing. Consensus determinism was taken to force a single-thread launch and forfeit the GPU. It does not: determinism constrains ordering WITHIN a book and says nothing across books, so one thread per book — each matching its taker stream in strict price-time priority, bit-for-bit re-executable, millions of threads — saturates the accelerator with every book deterministic. Restored at the later versions across all 27 files: the accounting section, the CLOB matcher, lightspeed-dex, lp-306, lp-308, lp-137, p3q-corona, the precompile engineering sections and the FHE orderbook application. Paper builds, 23 pages, no errors. Co-authored-by: Hanzo Dev <[email protected]>
73 lines
3.7 KiB
TeX
73 lines
3.7 KiB
TeX
\section{Benchmarks}
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\label{sec:benchmarks}
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This section consolidates the measured results from Sections~\ref{sec:gpu-matching},
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\ref{sec:settlement}, and~\ref{sec:rollup} into one table, states the hardware and method,
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and is explicit about which numbers are measured and which are aggregations or projections.
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\subsection{Hardware and method}
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\begin{itemize}
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\item \textbf{AMD Radeon 8060S} (coalesced SoA preload; fastest matcher measured).
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\item \textbf{NVIDIA GB10} (Grace-Blackwell, 128\,GB unified memory, \texttt{sm\_121},
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CUDA 13).
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\item \textbf{Apple M4 Max} (128\,GB unified memory, Metal).
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\item \textbf{Apple M1 Max} (Go reference, CPU settlement, verifier rates).
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\end{itemize}
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Matching and settlement throughput are reported as sustained rates over runs of tens of
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millions of operations, with the GPU matching figures gated by byte-exact parity against the
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CPU oracle (Section~\ref{sec:gpu-matching}). We report per-match latency where it is the
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governing quantity. No figure in this paper is taken from a simulation or scaled by a fudge
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factor.
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\subsection{Consolidated results}
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\begin{table}[H]
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\centering
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\renewcommand{\arraystretch}{1.3}
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\begin{tabular}{p{4.4cm} l r l}
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\toprule
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\textbf{Axis / quantity} & \textbf{Platform} & \textbf{Measured} & \textbf{Status} \\
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\midrule
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Matching (coalesced SoA) & AMD Radeon 8060S & 12.76\,B orders/s & measured \\
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Matching (coalesced SoA) & NVIDIA GB10 & 9.13\,B orders/s & measured \\
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Matching (un-coalesced) & NVIDIA GB10 & 1.54\,B orders/s & measured \\
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Matching (coalesced SoA) & Apple M4 Max & 5.60\,B orders/s & measured \\
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Matching (coalesced SoA) & Apple M1 Max & 2.80\,B orders/s & measured \\
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Conflict detection ($O(N)$) & M1 Max (CPU) & 2.2\,M fills/s & measured \\
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GPU conflict commit order & M4 (WGSL) & byte-identical to CPU & measured \\
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Market-sharded settle (8) & M1 Max (CPU) & $\sim$0.39\,M fills/s & measured \\
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P3Q verify (ML-DSA-65) & M1 Max (CPU) & 4{,}714 verifies/s & measured \\
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\texttt{starkfri} verify (toy AIR) & M1 Max (CPU) & 986 verifies/s & measured \\
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\midrule
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Matching (two-node fabric) & GB10 $\times$2 & 21.9\,B orders/s & aggregation \\
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$10^{9}$ settled-tx/s finality & P3Q, $K{=}10^{4}$, $M{=}22$ & $1.04\times10^{9}$ & finality model \\
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\bottomrule
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\end{tabular}
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\caption{Consolidated measured results across the three axes, with each row labeled
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measured, an aggregation of measured single-node rates, or a finality model that combines a
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measured verify rate with a stated batch size. Single-device matching is measured in the
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billions of orders/sec; the two-node fabric row is a linear aggregation, and the finality
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row is a model, both labeled accordingly.}
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\label{tab:consolidated}
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\end{table}
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\subsection{The two levers, restated}
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The tuned matcher combines two compounding levers: the Knuth Algorithm~D division (per lane,
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$\sim$8--12$\times$ over 512-iteration bit-serial, Table~\ref{tab:division}) and a coalesced
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structure-of-arrays arena layout that makes the kernel throughput-bound rather than
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latency-bound. An earlier draft, benchmarking an un-coalesced kernel, reported the matcher as
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dependency-latency bound at hundreds of millions of matches/s; the coalesced layout lifts
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sustained throughput into the billions of orders/sec per device---9.13\,B on a GB10 and
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12.76\,B on an AMD Radeon 8060S (Table~\ref{tab:gpu-throughput}).
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\subsection{What we do not claim}
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We do not claim an end-to-end latency derived from invented co-location round-trips, or any
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uptime statistic from a deployment we did not run. The single-device matching rates are
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measured and byte-parity-gated; fleet and fabric aggregation
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(Section~\ref{subsec:billion-matching}) scales them linearly, and settlement finality is a
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separate axis (Section~\ref{sec:rollup}).
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