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Quasar Horizon (consensus composition over Pulsar / ML-DSA / BLS lanes
under Prism + LSS lifecycle), Warp 2.0 (Pulse-backed cross-chain envelope
with forward-only v1->v2 migration and lattigo ReadUint64Slice DoS fix),
benchmark report (microbench, reshare, activation, Warp 2.0 verify, Prism
composition, GPU headroom, cross-WAN latency), and NIST IR 8214C-style
submission package (spec, parameter sets, domain separation, serialization,
reference-impl pointers, evaluation report, security analysis, side-channel
considerations).
All four deliverables compile cleanly via pdflatex+bibtex and reference
the canonical proof bucket files at proofs/{definitions,pulsar,lss,quasar}.
No duplication of proof bodies; cite by file path.
82 lines
2.4 KiB
TeX
82 lines
2.4 KiB
TeX
\section{Empirical Evaluation}
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\label{sec:evaluation}
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\subsection{Gate Performance}
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\begin{table}[h]
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\centering
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\begin{tabular}{@{}lrr@{}}
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\toprule
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\textbf{Gate} & \textbf{Time (ms)} & \textbf{Ciphertext Size (bytes)} \\
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\midrule
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NOT & 0.001 & 8,208 \\
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AND & 12.3 & 8,208 \\
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OR & 12.1 & 8,208 \\
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XOR & 12.4 & 8,208 \\
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NAND & 12.2 & 8,208 \\
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NOR & 12.3 & 8,208 \\
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XNOR & 12.5 & 8,208 \\
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MUX & 24.6 & 8,208 \\
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MAJORITY & 12.4 & 8,208 \\
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\bottomrule
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\end{tabular}
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\caption{TFHE gate evaluation performance (single core)}
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\label{tab:gate-perf}
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\end{table}
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\subsection{Multi-Bit Operations}
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\begin{table}[h]
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\centering
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\begin{tabular}{@{}lrr@{}}
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\toprule
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\textbf{Operation} & \textbf{Bits} & \textbf{Time (ms)} \\
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\midrule
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Addition (uint32) & 32 & 780 \\
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Comparison (uint32) & 32 & 395 (CMPCOMBINE) \\
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Multiplication (uint8) & 8 & 1,200 \\
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Equality (uint32) & 32 & 420 \\
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\bottomrule
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\end{tabular}
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\caption{Multi-bit operation performance}
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\label{tab:multibit}
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\end{table}
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\subsection{Threshold Decryption}
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\begin{table}[h]
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\centering
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\begin{tabular}{@{}lrr@{}}
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\toprule
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\textbf{Threshold} & \textbf{Decryption Time} & \textbf{Communication} \\
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\midrule
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2-of-3 & 5ms & 24 KB \\
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3-of-5 & 12ms & 40 KB \\
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5-of-10 & 28ms & 80 KB \\
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\bottomrule
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\end{tabular}
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\caption{Threshold decryption performance}
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\label{tab:threshold-perf}
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\end{table}
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\subsection{F-Chain NTT primitive on Apple Metal}
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The F-Chain TFHE pipeline reduces every gate evaluation to NTT-domain
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multiplications. The Metal NTT kernel (\texttt{luxcpp/fhe}) reaches
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${\sim}23.63\times$ CPU at $N{=}4{,}096$, $B{=}128$ on Apple M1 Max
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(LP-137 Phase-2 roll-up, 2026-04-26 reproduction; Phase-3 unchanged).
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Smaller batches degrade gracefully: $9.0\times$ at $N{=}4{,}096$,
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$B{=}32$, and $6.2\times$ at $N{=}8{,}192$, $B{=}128$. This is one
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of three production workloads on the LP-137 substrate that beat CPU
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end-to-end (alongside C-Chain and B-Chain BLS aggregate batched
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verify) and is plausibly state-of-the-art on Apple Silicon for the
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TFHE NTT shape. The full empirical surface (CPU, Metal, MLX, CUDA,
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WGSL) is exercised by 2 174 gtest cases across the four backends
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that compile on each test host; CPU is the byte-equivalence ground
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truth that every backend is asserted against.
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%% -----------------------------------------------------------------------
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%% 8. CONCLUSION
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%% -----------------------------------------------------------------------
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