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papers/lux-tfhe/sections/07-empirical-evaluation.tex
zeekay 98343d238e papers: Mar-3 freeze deliverables for hybrid PQ consensus stack
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\section{Empirical Evaluation}
\label{sec:evaluation}
\subsection{Gate Performance}
\begin{table}[h]
\centering
\begin{tabular}{@{}lrr@{}}
\toprule
\textbf{Gate} & \textbf{Time (ms)} & \textbf{Ciphertext Size (bytes)} \\
\midrule
NOT & 0.001 & 8,208 \\
AND & 12.3 & 8,208 \\
OR & 12.1 & 8,208 \\
XOR & 12.4 & 8,208 \\
NAND & 12.2 & 8,208 \\
NOR & 12.3 & 8,208 \\
XNOR & 12.5 & 8,208 \\
MUX & 24.6 & 8,208 \\
MAJORITY & 12.4 & 8,208 \\
\bottomrule
\end{tabular}
\caption{TFHE gate evaluation performance (single core)}
\label{tab:gate-perf}
\end{table}
\subsection{Multi-Bit Operations}
\begin{table}[h]
\centering
\begin{tabular}{@{}lrr@{}}
\toprule
\textbf{Operation} & \textbf{Bits} & \textbf{Time (ms)} \\
\midrule
Addition (uint32) & 32 & 780 \\
Comparison (uint32) & 32 & 395 (CMPCOMBINE) \\
Multiplication (uint8) & 8 & 1,200 \\
Equality (uint32) & 32 & 420 \\
\bottomrule
\end{tabular}
\caption{Multi-bit operation performance}
\label{tab:multibit}
\end{table}
\subsection{Threshold Decryption}
\begin{table}[h]
\centering
\begin{tabular}{@{}lrr@{}}
\toprule
\textbf{Threshold} & \textbf{Decryption Time} & \textbf{Communication} \\
\midrule
2-of-3 & 5ms & 24 KB \\
3-of-5 & 12ms & 40 KB \\
5-of-10 & 28ms & 80 KB \\
\bottomrule
\end{tabular}
\caption{Threshold decryption performance}
\label{tab:threshold-perf}
\end{table}
\subsection{F-Chain NTT primitive on Apple Metal}
The F-Chain TFHE pipeline reduces every gate evaluation to NTT-domain
multiplications. The Metal NTT kernel (\texttt{luxcpp/fhe}) reaches
${\sim}23.63\times$ CPU at $N{=}4{,}096$, $B{=}128$ on Apple M1 Max
(LP-137 Phase-2 roll-up, 2026-04-26 reproduction; Phase-3 unchanged).
Smaller batches degrade gracefully: $9.0\times$ at $N{=}4{,}096$,
$B{=}32$, and $6.2\times$ at $N{=}8{,}192$, $B{=}128$. This is one
of three production workloads on the LP-137 substrate that beat CPU
end-to-end (alongside C-Chain and B-Chain BLS aggregate batched
verify) and is plausibly state-of-the-art on Apple Silicon for the
TFHE NTT shape. The full empirical surface (CPU, Metal, MLX, CUDA,
WGSL) is exercised by 2 174 gtest cases across the four backends
that compile on each test host; CPU is the byte-equivalence ground
truth that every backend is asserted against.
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%% 8. CONCLUSION
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