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zeekay
a1169a810e
The D side of the precompile/dex H1 rail-binding. The shared-memory object wire goes 60->61 bytes: rail(1)|owner(20)|asset(32)|amount(8), byte-identical to the precompile's exportedOutputSize9999. The rail tag is the lane the value travels (RailSwap=0 default / RailLP=1) and round-trips through the atomic core unchanged. - txs.AtomicOutput gains Rail; ImportTx/ExportTx.Verify enforce one-rail-per-leg (structural half, mirroring the asset bind). - encode/decodeExportedOutput carry the rail byte (decode now returns rail too). - executeImport binds the credited outputs' rail to the consumed UTXO's RECORDED rail (authoritative half; errImportMixedRails), so an import cannot re-lane value — a swap object onto the LP lane or vice-versa. - executeWithdraw (the LP collect/withdraw export) stamps RailLP; the fill/refund settlement exports (settleFromFills) stay RailSwap (zero default). New: TestNativeRail_ImportRejectsRailMismatch (both directions) + TestNativeRail_ImportAcceptsMatchingRail (positive control). Wire-parity canary TestNativeSeam_WireMatchesPrecompile asserts byte-identity on BOTH rails. LP-seam round-trip + conservation/redteam offset helpers updated to the 61-byte wire. CGO_ENABLED=0 GOWORK=off go test ./dexvm/... green.