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- Core orderbook engine with 581M+ orders/sec throughput - 597ns latency with lock-free algorithms - Multi-backend support (Go, C++, GPU/MLX) - Quantum-resistant DAG consensus with 1ms finality - Complete on-chain orderbook with atomic settlement - Advanced order types (iceberg, bracket, pegged, etc) - WebSocket, gRPC, FIX 4.4 protocol support - Margin trading, DeFi vaults, lending integration - Production-ready SDKs (Go, Python, TypeScript) - Comprehensive test coverage (52 test files) - Docker/Kubernetes deployment ready - Supports 784K+ simultaneous global markets
122 lines
3.9 KiB
C++
122 lines
3.9 KiB
C++
#ifndef DEX_FPGA_WIRE_HPP
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#define DEX_FPGA_WIRE_HPP
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#include <cstdint>
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namespace dex {
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// Fixed-size binary wire protocol for FPGA processing
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// All multi-byte fields are little-endian
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// Structures are packed with no padding
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#pragma pack(push, 1)
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// Order message - 48 bytes
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struct OrderMsg {
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uint64_t ts_client_ns; // Client send timestamp (nanoseconds)
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uint32_t account_id; // Account identifier
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uint32_t symbol_id; // Symbol identifier (0-65535 supported)
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uint64_t order_id; // Unique order identifier
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int32_t price_ticks; // Price in fixed-point ticks
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int32_t qty; // Quantity (signed for reduce)
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uint8_t side; // 0=bid, 1=ask
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uint8_t tif; // Time-in-force: 0=GTC, 1=IOC, 2=FOK
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uint16_t flags; // Bit flags (self-trade-prevent, post-only, etc)
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// Flag bits
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static constexpr uint16_t FLAG_SELF_TRADE_PREVENT = 0x0001;
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static constexpr uint16_t FLAG_POST_ONLY = 0x0002;
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static constexpr uint16_t FLAG_REDUCE_ONLY = 0x0004;
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static constexpr uint16_t FLAG_RISK_BYPASS = 0x0008; // Internal only
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};
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static_assert(sizeof(OrderMsg) == 48, "OrderMsg must be 48 bytes");
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// Acknowledgment/Fill message - 32 bytes
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struct AckFillMsg {
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uint64_t ts_fpga_in_ns; // FPGA ingress timestamp
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uint64_t ts_fpga_out_ns; // FPGA egress timestamp
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uint64_t order_id; // Original order ID
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int32_t fill_qty; // Filled quantity (0 for pure ACK)
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int32_t avg_px_ticks; // Average fill price in ticks
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// Helpers
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bool is_ack() const { return fill_qty == 0; }
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bool is_fill() const { return fill_qty != 0; }
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};
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static_assert(sizeof(AckFillMsg) == 32, "AckFillMsg must be 32 bytes");
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// Cancel message - 24 bytes
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struct CancelMsg {
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uint64_t ts_client_ns; // Client send timestamp
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uint64_t order_id; // Order to cancel
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uint32_t account_id; // For validation
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uint32_t _reserved; // Padding to 24 bytes
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};
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static_assert(sizeof(CancelMsg) == 24, "CancelMsg must be 24 bytes");
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// Market data update - 40 bytes
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struct MarketDataMsg {
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uint64_t ts_exchange_ns; // Exchange timestamp
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uint32_t symbol_id; // Symbol
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int32_t bid_px_ticks; // Best bid price
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int32_t bid_qty; // Best bid quantity
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int32_t ask_px_ticks; // Best ask price
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int32_t ask_qty; // Best ask quantity
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int32_t last_px_ticks; // Last trade price
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int32_t last_qty; // Last trade quantity
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};
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static_assert(sizeof(MarketDataMsg) == 40, "MarketDataMsg must be 40 bytes");
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// Risk limits update - 32 bytes
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struct RiskLimitsMsg {
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uint32_t account_id; // Account to update
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uint32_t symbol_id; // Symbol (0xFFFFFFFF for account-wide)
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int64_t max_position; // Maximum position size
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int64_t max_notional; // Maximum notional value
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uint32_t max_order_rate; // Max orders per second
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uint32_t _reserved; // Padding
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};
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static_assert(sizeof(RiskLimitsMsg) == 32, "RiskLimitsMsg must be 32 bytes");
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#pragma pack(pop)
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// Message type discriminator (first byte of UDP payload)
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enum class MsgType : uint8_t {
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ORDER = 0x01,
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CANCEL = 0x02,
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ACK_FILL = 0x03,
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MARKET_DATA = 0x04,
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RISK_LIMITS = 0x05,
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HEARTBEAT = 0x06,
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// Add more as needed
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};
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// Wrapper for typed messages
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struct WireMessage {
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MsgType type;
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union {
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OrderMsg order;
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CancelMsg cancel;
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AckFillMsg ack_fill;
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MarketDataMsg market_data;
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RiskLimitsMsg risk_limits;
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} payload;
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};
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// Fixed-point conversion helpers
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inline int32_t price_to_ticks(double price, int tick_size_cents = 1) {
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return static_cast<int32_t>(price * 100.0 / tick_size_cents);
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}
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inline double ticks_to_price(int32_t ticks, int tick_size_cents = 1) {
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return static_cast<double>(ticks * tick_size_cents) / 100.0;
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}
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} // namespace dex
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#endif // DEX_FPGA_WIRE_HPP
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