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d30631df7a
- Core orderbook engine with 581M+ orders/sec throughput - 597ns latency with lock-free algorithms - Multi-backend support (Go, C++, GPU/MLX) - Quantum-resistant DAG consensus with 1ms finality - Complete on-chain orderbook with atomic settlement - Advanced order types (iceberg, bracket, pegged, etc) - WebSocket, gRPC, FIX 4.4 protocol support - Margin trading, DeFi vaults, lending integration - Production-ready SDKs (Go, Python, TypeScript) - Comprehensive test coverage (52 test files) - Docker/Kubernetes deployment ready - Supports 784K+ simultaneous global markets
401 lines
12 KiB
Systemverilog
401 lines
12 KiB
Systemverilog
/**
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* NIC-Resident Order Processing Pipeline
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*
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* Wire-to-wire ultra-low latency implementation for
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* AMD Alveo U50/U55C or Intel Agilex-7 with 100GbE
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*/
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module nic_top #(
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parameter ENABLE_100G = 1,
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parameter ENABLE_PTP = 1,
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parameter NUM_SYMBOLS = 256,
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parameter BOOK_DEPTH = 32
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)(
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// Clock and reset
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input logic clk_100g, // 100GbE clock (390.625 MHz)
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input logic clk_core, // Core clock (250 MHz)
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input logic clk_ptp, // PTP clock (156.25 MHz)
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input logic rst_n,
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// 100GbE MAC interface (AXI-Stream)
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input logic [511:0] rx_axis_tdata,
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input logic [63:0] rx_axis_tkeep,
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input logic rx_axis_tvalid,
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output logic rx_axis_tready,
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input logic rx_axis_tlast,
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input logic [15:0] rx_axis_tuser,
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output logic [511:0] tx_axis_tdata,
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output logic [63:0] tx_axis_tkeep,
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output logic tx_axis_tvalid,
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input logic tx_axis_tready,
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output logic tx_axis_tlast,
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output logic [15:0] tx_axis_tuser,
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// PTP timestamp interface
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input logic [63:0] ptp_timestamp_ns,
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input logic ptp_timestamp_valid,
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// HBM interface (AXI4)
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output logic [31:0] m_axi_awaddr,
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output logic [7:0] m_axi_awlen,
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output logic m_axi_awvalid,
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input logic m_axi_awready,
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output logic [511:0] m_axi_wdata,
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output logic [63:0] m_axi_wstrb,
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output logic m_axi_wlast,
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output logic m_axi_wvalid,
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input logic m_axi_wready,
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input logic [1:0] m_axi_bresp,
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input logic m_axi_bvalid,
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output logic m_axi_bready,
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// Control/Status interface (AXI-Lite)
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input logic [31:0] s_axil_awaddr,
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input logic s_axil_awvalid,
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output logic s_axil_awready,
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input logic [31:0] s_axil_wdata,
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input logic [3:0] s_axil_wstrb,
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input logic s_axil_wvalid,
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output logic s_axil_wready,
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output logic [1:0] s_axil_bresp,
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output logic s_axil_bvalid,
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input logic s_axil_bready,
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// Statistics outputs
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output logic [63:0] stat_orders_processed,
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output logic [63:0] stat_orders_matched,
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output logic [63:0] stat_latency_cycles,
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output logic [31:0] stat_error_count
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);
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// Internal signals
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logic [511:0] packet_data;
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logic packet_valid;
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logic packet_ready;
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logic [15:0] packet_len;
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logic [63:0] rx_timestamp;
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// Order message decoded
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logic [63:0] order_timestamp;
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logic [31:0] order_account_id;
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logic [31:0] order_symbol_id;
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logic [63:0] order_id;
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logic [31:0] order_price;
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logic [31:0] order_qty;
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logic [7:0] order_side;
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logic [7:0] order_tif;
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logic [15:0] order_flags;
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logic order_valid;
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logic order_ready;
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// Match results
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logic [63:0] match_order_id;
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logic [31:0] match_qty;
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logic [31:0] match_price;
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logic [63:0] match_timestamp_in;
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logic [63:0] match_timestamp_out;
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logic match_valid;
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logic match_ready;
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// =========================================================================
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// RX Path: Packet Parser
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// =========================================================================
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packet_parser parser_inst (
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.clk(clk_100g),
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.rst_n(rst_n),
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// From MAC
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.rx_tdata(rx_axis_tdata),
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.rx_tkeep(rx_axis_tkeep),
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.rx_tvalid(rx_axis_tvalid),
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.rx_tready(rx_axis_tready),
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.rx_tlast(rx_axis_tlast),
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// PTP timestamp
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.ptp_timestamp(ptp_timestamp_ns),
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// Parsed output
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.packet_data(packet_data),
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.packet_valid(packet_valid),
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.packet_ready(packet_ready),
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.packet_len(packet_len),
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.rx_timestamp(rx_timestamp)
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);
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// =========================================================================
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// Order Decoder (Fixed 48-byte messages)
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// =========================================================================
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order_decoder decoder_inst (
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.clk(clk_100g),
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.rst_n(rst_n),
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// From parser
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.packet_data(packet_data),
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.packet_valid(packet_valid),
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.packet_ready(packet_ready),
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.rx_timestamp(rx_timestamp),
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// Decoded order
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.order_timestamp(order_timestamp),
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.order_account_id(order_account_id),
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.order_symbol_id(order_symbol_id),
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.order_id(order_id),
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.order_price(order_price),
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.order_qty(order_qty),
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.order_side(order_side),
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.order_tif(order_tif),
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.order_flags(order_flags),
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.order_valid(order_valid),
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.order_ready(order_ready)
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);
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// =========================================================================
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// Risk Check Module (Single-cycle)
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// =========================================================================
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wire risk_pass;
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wire [31:0] risk_max_position;
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wire [31:0] risk_max_notional;
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risk_checker risk_inst (
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.clk(clk_100g),
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.rst_n(rst_n),
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// Order input
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.account_id(order_account_id),
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.symbol_id(order_symbol_id),
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.price(order_price),
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.qty(order_qty),
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.side(order_side),
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// Risk decision (combinational)
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.risk_pass(risk_pass),
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// Configuration (from AXI-Lite)
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.max_position(risk_max_position),
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.max_notional(risk_max_notional)
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);
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// =========================================================================
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// Matching Engine Core
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// =========================================================================
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matching_engine #(
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.NUM_SYMBOLS(NUM_SYMBOLS),
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.BOOK_DEPTH(BOOK_DEPTH)
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) matcher_inst (
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.clk(clk_core),
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.rst_n(rst_n),
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// Order input
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.order_id(order_id),
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.symbol_id(order_symbol_id[7:0]), // Support 256 symbols
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.price(order_price),
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.qty(order_qty),
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.side(order_side[0]), // 0=buy, 1=sell
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.tif(order_tif[1:0]), // 0=GTC, 1=IOC, 2=FOK
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.valid(order_valid & risk_pass),
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.ready(order_ready),
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// Match output
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.match_order_id(match_order_id),
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.match_qty(match_qty),
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.match_price(match_price),
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.match_timestamp_in(order_timestamp),
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.match_timestamp_out(match_timestamp_out),
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.match_valid(match_valid),
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.match_ready(match_ready),
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// HBM interface for book storage
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.hbm_addr(m_axi_awaddr),
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.hbm_wdata(m_axi_wdata),
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.hbm_wvalid(m_axi_wvalid),
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.hbm_wready(m_axi_wready)
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);
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// =========================================================================
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// TX Path: Response Builder
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// =========================================================================
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response_builder builder_inst (
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.clk(clk_100g),
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.rst_n(rst_n),
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// Match input
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.match_order_id(match_order_id),
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.match_qty(match_qty),
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.match_price(match_price),
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.match_timestamp_in(match_timestamp_in),
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.match_timestamp_out(match_timestamp_out),
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.match_valid(match_valid),
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.match_ready(match_ready),
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// To MAC
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.tx_tdata(tx_axis_tdata),
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.tx_tkeep(tx_axis_tkeep),
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.tx_tvalid(tx_axis_tvalid),
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.tx_tready(tx_axis_tready),
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.tx_tlast(tx_axis_tlast)
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);
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// =========================================================================
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// Statistics Collection
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// =========================================================================
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always_ff @(posedge clk_core) begin
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if (!rst_n) begin
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stat_orders_processed <= 64'b0;
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stat_orders_matched <= 64'b0;
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stat_latency_cycles <= 64'b0;
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stat_error_count <= 32'b0;
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end else begin
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// Count processed orders
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if (order_valid & order_ready) begin
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stat_orders_processed <= stat_orders_processed + 1;
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end
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// Count matched orders
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if (match_valid & match_ready & (match_qty != 0)) begin
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stat_orders_matched <= stat_orders_matched + 1;
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end
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// Track latency (simplified - would use histogram in production)
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if (match_valid & match_ready) begin
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stat_latency_cycles <= match_timestamp_out - match_timestamp_in;
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end
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// Count errors (risk failures, etc)
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if (order_valid & !risk_pass) begin
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stat_error_count <= stat_error_count + 1;
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end
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end
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end
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// =========================================================================
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// Control Interface (AXI-Lite)
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// =========================================================================
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control_registers ctrl_inst (
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.clk(clk_core),
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.rst_n(rst_n),
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// AXI-Lite slave
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.s_axil_awaddr(s_axil_awaddr),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata(s_axil_wdata),
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.s_axil_wstrb(s_axil_wstrb),
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.s_axil_wvalid(s_axil_wvalid),
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.s_axil_wready(s_axil_wready),
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.s_axil_bresp(s_axil_bresp),
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.s_axil_bvalid(s_axil_bvalid),
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.s_axil_bready(s_axil_bready),
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// Configuration outputs
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.risk_max_position(risk_max_position),
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.risk_max_notional(risk_max_notional)
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);
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endmodule
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// =========================================================================
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// Sub-module: Packet Parser
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// =========================================================================
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module packet_parser (
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input logic clk,
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input logic rst_n,
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// MAC interface
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input logic [511:0] rx_tdata,
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input logic [63:0] rx_tkeep,
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input logic rx_tvalid,
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output logic rx_tready,
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input logic rx_tlast,
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// PTP timestamp
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input logic [63:0] ptp_timestamp,
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// Parsed output
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output logic [511:0] packet_data,
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output logic packet_valid,
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input logic packet_ready,
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output logic [15:0] packet_len,
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output logic [63:0] rx_timestamp
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);
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// Simple pass-through for now - would parse UDP in production
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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packet_valid <= 1'b0;
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rx_tready <= 1'b1;
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end else begin
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rx_tready <= packet_ready;
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if (rx_tvalid && rx_tready) begin
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packet_data <= rx_tdata;
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packet_valid <= rx_tlast; // Assume single-beat packets
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packet_len <= 16'd48; // Fixed order size
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rx_timestamp <= ptp_timestamp;
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end else if (packet_ready) begin
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packet_valid <= 1'b0;
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end
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end
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end
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endmodule
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// =========================================================================
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// Sub-module: Order Decoder
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// =========================================================================
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module order_decoder (
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input logic clk,
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input logic rst_n,
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// Packet input
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input logic [511:0] packet_data,
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input logic packet_valid,
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output logic packet_ready,
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input logic [63:0] rx_timestamp,
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// Decoded order output
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output logic [63:0] order_timestamp,
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output logic [31:0] order_account_id,
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output logic [31:0] order_symbol_id,
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output logic [63:0] order_id,
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output logic [31:0] order_price,
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output logic [31:0] order_qty,
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output logic [7:0] order_side,
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output logic [7:0] order_tif,
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output logic [15:0] order_flags,
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output logic order_valid,
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input logic order_ready
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);
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// Decode 48-byte order message from packet
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// Assuming order starts at byte 42 (after Eth+IP+UDP headers)
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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order_valid <= 1'b0;
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packet_ready <= 1'b1;
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end else begin
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packet_ready <= order_ready;
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if (packet_valid && packet_ready) begin
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// Extract fields (little-endian)
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order_timestamp <= packet_data[335:272]; // Bytes 42-49
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order_account_id <= packet_data[271:240]; // Bytes 50-53
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order_symbol_id <= packet_data[239:208]; // Bytes 54-57
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order_id <= packet_data[207:144]; // Bytes 58-65
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order_price <= packet_data[143:112]; // Bytes 66-69
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order_qty <= packet_data[111:80]; // Bytes 70-73
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order_side <= packet_data[79:72]; // Byte 74
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order_tif <= packet_data[71:64]; // Byte 75
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order_flags <= packet_data[63:48]; // Bytes 76-77
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order_valid <= 1'b1;
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end else if (order_ready) begin
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order_valid <= 1'b0;
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end
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end
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end
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endmodule |