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zeekay
d14b104790
Three orthogonal additions, one wire format. v2 package — generic ad-hoc schema dispatch (~/work/lux/zap/v2): - README + IMPOSSIBILITY + BENCH_RESULTS document the v1↔v2 split. - builder/field/iter/list/pool/registry/schema/view + codegen package emit v1-equivalent fast paths from declarative .zap sources. - _compile_fail_test/ + examples/ cover negative and positive cases. - v2_test.go exercises the generic dispatch path. - doc.go in v1 marks v1 deprecated for *new* schema authoring; existing v1 buffers stay parseable by both v1 and v2. bufpool — pooled read slabs (bufpool.go + bufpool_test.go): - Message gains optional *bufRef; Release() returns the slab to its pool when sourced from the pooled read path, GC-managed otherwise. - ParseHeader returns (data, rootOffset) without allocating *Message, used by zapv2 to avoid two allocations per parse. - bench_read_test.go + node_quic_stream_test.go cover both paths. Transport allocator + UMA/RDMA cgo (transport/*): - Transport.Caps()/Buffer interface: capability + slab-typed buffer contract. Bytes() vs DevicePtr() decoupled so UMA and GPUDirect can share the same call surface. - DPDK PMD + GPUDirect RDMA + CUDA UMA real cgo backends gated behind build tags; stub paths remain default on darwin / non-Linux. - transport_test.go covers Caps reporting + Buffer lifecycle on the default transport. LLM.md + go.mod follow the additions.
67 lines
2.5 KiB
C
67 lines
2.5 KiB
C
// Copyright (C) 2025-2026, Lux Industries Inc. All rights reserved.
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// See the file LICENSE for licensing terms.
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//
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// Host-side C API for the GPUDirect RDMA probe + DMA-buf MR registration.
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// The data-plane (QP create / post_send / poll_cq) is intentionally
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// minimal — what changes the wire is the MR registration, which lets the
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// NIC DMA straight into GPU memory.
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#ifndef LUX_ZAP_TRANSPORT_GPUDIRECT_RDMA_H
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#define LUX_ZAP_TRANSPORT_GPUDIRECT_RDMA_H
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#include <stddef.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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// luxzap_gd_probe reports whether GPUDirect RDMA's prerequisites are
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// satisfied on this host:
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//
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// bit 0 (0x01) : at least one ibverbs device is open-able
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// bit 1 (0x02) : at least one device reports IBV_DEVICE_RAW_PACKET
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// (Mellanox CX-6/7 etc.)
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// bit 2 (0x04) : nvidia_peermem (or its successor nvidia-peermem)
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// kernel module appears in /proc/modules
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// bit 3 (0x08) : at least one CUDA device is usable
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//
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// Returns 0 when ALL four bits would be set; otherwise returns a
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// negative value whose lower nibble is the bitmask of bits that WERE
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// set, OR'd with 0x80 to distinguish from a clean 0.
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//
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// Operators read the returned bitmask via `negate-and-mask 0x7f` to see
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// which prereq is missing.
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int luxzap_gd_probe(void);
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// luxzap_gd_open opens the first ibverbs device that reports
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// IBV_DEVICE_RAW_PACKET. Returns a non-zero opaque handle on success
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// (passed to subsequent calls) and writes the device name into
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// `name_buf` (caller-allocated, name_buflen bytes, NUL-terminated).
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// Returns 0 on failure with errno set.
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uintptr_t luxzap_gd_open(char* name_buf, size_t name_buflen);
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// luxzap_gd_close releases an opened context.
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void luxzap_gd_close(uintptr_t handle);
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// luxzap_gd_reg_dmabuf_mr registers a chunk of GPU memory (DMA-buf fd
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// exported from CUDA) as an ibverbs Memory Region. Returns 0 on success
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// (the MR handle is written to *out_mr_handle), or a negative errno
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// otherwise. The NIC can DMA into this region without bouncing through
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// CPU memory.
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//
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// `offset` and `size` are in bytes. `access_flags` is the bitmask of
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// IBV_ACCESS_* flags the caller wants.
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int luxzap_gd_reg_dmabuf_mr(uintptr_t handle, int dmabuf_fd,
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uint64_t offset, uint64_t size,
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int access_flags,
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uintptr_t* out_mr_handle);
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// luxzap_gd_dereg_mr deregisters a previously-registered MR.
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int luxzap_gd_dereg_mr(uintptr_t mr_handle);
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#ifdef __cplusplus
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}
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#endif
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#endif // LUX_ZAP_TRANSPORT_GPUDIRECT_RDMA_H
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