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Merge pull request #3564 from amd-jnovotny/peak-tflops-typo-roc62x

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Fix typo for TFLOPs metric in MI250 architecture page: cherry pick to roc-6.2.x
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Sam Wu
2024-08-12 11:27:40 -06:00
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parent ad861e768c 82a98ae3f4
commit 8fd6278863
1 changed files with 2 additions and 2 deletions
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docs/conceptual/gpu-arch/mi250.md
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@@ -33,8 +33,8 @@ Units (CU). The MI250 GCD has 104 active CUs. Each compute unit is further
subdivided into four SIMD units that process SIMD instructions of 16 data
elements per instruction (for the FP64 data type). This enables the CU to
process 64 work items (a so-called “wavefront”) at a peak clock frequency of 1.7
GHz. Therefore, the theoretical maximum FP64 peak performance per GCD is 45.3
TFLOPS for vector instructions. The MI250 compute units also provide specialized
GHz. Therefore, the theoretical maximum FP64 peak performance per GCD is 22.6
TFLOPS for vector instructions. This equates to 45.3 TFLOPS for vector instructions for both GCDs together. The MI250 compute units also provide specialized
execution units (also called matrix cores), which are geared toward executing
matrix operations like matrix-matrix multiplications. For FP64, the peak
performance of these units amounts to 90.5 TFLOPS.