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docs: align cc/attestation refs to luxfi/cc v0.2.0 (6 production vendors)

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- architecture.mdx, wallet/security.mdx: v0.1.0 -> v0.2.0; note the six
  production CPU/GPU vendors (SEV-SNP, TDX, SGX, nvtrust, Nitro, ARM CCA)
- confidential-compute.mdx: fix Nitro Vendor string aws.nitro -> aws.nitro.enclaves
  (matches attest/nitro.go nitroVendor)

Verified against luxfi/[email protected] attest/{doc.go,verifier.go,*.go}: six Kinds,
one self-registering registry, fail-closed Dispatch.
This commit is contained in:
zeekay
2026-06-27 15:43:40 -07:00
parent 8b26613ade
commit f30f9431df
3 changed files with 6 additions and 5 deletions
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apps/docs/content/docs/architecture.mdx
+4 -3
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@@ -96,9 +96,10 @@ core depends on **none** of the extensions.
extension. Explicitly **not** required by the threshold core and **not** used on
the permissionless/dealerless production signing path; the dependency direction
is one-way (`tee → pulsar/corona/mpc`, never the reverse).
- **`luxfi/cc`** (v0.1.0) — one attestation verifier, with orthogonal hardware
`Kind`s, shared by MPC custody, TEE custody, and confidential AI. It depends on
none of them. See [Confidential Compute](/confidential-compute).
- **`luxfi/cc`** (v0.2.0) — one attestation verifier with orthogonal hardware
`Kind`s, six production CPU/GPU vendors (AMD SEV-SNP, Intel TDX, Intel SGX,
NVIDIA nvtrust, AWS Nitro, ARM CCA), shared by MPC custody, TEE custody, and
confidential AI. It depends on none of them. See [Confidential Compute](/confidential-compute).
This is the seam: the permissionless chain runs on the dealerless PQ core alone;
TEE and external-MPC custody are accelerators an operator opts into, never trust
apps/docs/content/docs/confidential-compute.mdx
+1 -1
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@@ -94,7 +94,7 @@ with the same composite hash produced byte-identical verifier output.
| Field | Meaning |
|-------|---------|
| `Kind` | The verifier that produced the report |
| `Vendor` | Canonical issuer (`amd.sev.snp`, `intel.tdx`, `intel.sgx.dcap`, `nvidia.nvtrust.local`/`.nras`, `arm.cca`, `aws.nitro`) |
| `Vendor` | Canonical issuer (`amd.sev.snp`, `intel.tdx`, `intel.sgx.dcap`, `nvidia.nvtrust.local`/`.nras`, `arm.cca`, `aws.nitro.enclaves`) |
| `Measurement` | The launch-measurement the hardware attests to (SEV-SNP 48-byte LD digest; TDX SHA-384(MRTD‖RTMR0..3); SGX `MRENCLAVE`; NVIDIA per-driver+VBIOS RIM digest; ARM CCA RIM; Nitro PCR0) |
| `ReportData` | The 64-byte caller-supplied challenge field — the caller proved freshness by binding their nonce here **before** attestation |
| `ChipID` | Silicon identity (SEV-SNP VCEK `CHIP_ID`; TDX/SGX PCK descriptor; per-GPU UUID; Nitro/CCA platform instance id) |
apps/docs/content/docs/wallet/security.mdx
+1 -1
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@@ -63,7 +63,7 @@ TEE custody extension, composed over a shared attestation verifier.
|--------|-----|------|
| [`luxfi/mpc`](https://github.com/luxfi/mpc) | v1.16.0 | Threshold MPC custody — **CGGMP21** (secp256k1 ECDSA) and **FROST** (Schnorr / ed25519). t-of-n signing, DKG, resharing, refresh, and a policy engine. |
| [`luxfi/tee`](https://github.com/luxfi/tee) | v0.1.0 | **Optional** TEE-backed threshold-signing custody extension (attested enclave). One-way dependency on the signing kernels; **not** required by the threshold core. |
| [`luxfi/cc`](https://github.com/luxfi/cc) | v0.1.0 | One attestation verifier the custody modules call before releasing a key share into hardware. See [Confidential Compute](/confidential-compute). |
| [`luxfi/cc`](https://github.com/luxfi/cc) | v0.2.0 | One attestation verifier (six production CPU/GPU vendors: AMD SEV-SNP, Intel TDX, Intel SGX, NVIDIA nvtrust, AWS Nitro, ARM CCA) the custody modules call before releasing a key share into hardware. See [Confidential Compute](/confidential-compute). |
<Callout>
The optional extension model: `luxfi/mpc` (MPC custody) and `luxfi/tee` (TEE